Location: Palo Alto, United States
📍
Location:
Palo Alto, CA
📄
Employment Type:
Contract
🏢
Work Arrangement:
On-site
🚀
Start Date:
TBD
💰
Compensation:
TBD — based on skills and experience
Important Screening Requirements
5+ years of experience
in post-silicon characterization, high-speed I/O (HSIO) validation, or memory electrical validation.
Hands-on experience characterizing
high-speed SerDes PHYs
, particularly PCIe.
Experience measuring
eye diagrams, jitter, bit error rate (BER), and S-parameters
.
Proficiency with high-speed oscilloscopes, bit error rate testers (BERT), and VNA/TDR equipment.
Ability to read and interpret schematics and PCB layouts.
Experience debugging electrical issues directly at the probe point.
Python scripting experience for laboratory test automation.
Background in semiconductor, silicon, or systems companies, including SoC, GPU, networking, storage, or automotive compute.
Must be willing to work
on-site in Palo Alto, CA
.
About the Role
We are seeking a hands-on
PCIe Characterization Engineer
to perform post-silicon electrical characterization and validation of high-speed SerDes physical-layer interfaces in a laboratory environment.
The role focuses on conducting high-speed electrical measurements, analyzing signal integrity, and validating silicon performance. You will independently operate laboratory equipment, troubleshoot signal-level issues, interpret hardware schematics and PCB layouts, and automate characterization workflows using Python.
The successful candidate will have direct experience with high-speed interface characterization and the practical skills needed to investigate electrical performance issues at the measurement and probe points.
What We’re Looking For
We’re looking for an experienced
post-silicon characterization or HSIO validation engineer
with strong hands-on laboratory skills and practical knowledge of high-speed electrical measurements.
The ideal candidate can independently perform eye, jitter, BER, and S-parameter measurements; operate high-speed test equipment; interpret schematics and layouts; and troubleshoot signal integrity issues directly in the lab.
Strong candidates will combine experience with
PCIe and SerDes interfaces, high-speed measurement instrumentation, electrical debugging, and Python-based lab automation
.
Key Responsibilities
Post-Silicon Characterization & Validation
Perform post-silicon electrical characterization of high-speed SerDes PHYs, including:
PCIe
Ethernet
UFS
LPDDR5
Support high-speed interface validation and investigate electrical performance issues.
Analyze characterization results to assess high-speed interface performance.
Identify and troubleshoot signal-level issues during testing.
High-Speed Electrical Measurements
Conduct
eye diagram, jitter, bit error rate (BER), and S-parameter measurements
.
Independently operate laboratory measurement equipment, including:
High-speed oscilloscopes
Bit error rate testers (BERT)
Vector network analyzers (VNA)
Time-domain reflectometry (TDR) equipment
Analyze measurement data to evaluate electrical performance and signal integrity.
Document test configurations, measurement results, and characterization findings.
Schematic Analysis & Electrical Debugging
Read and interpret electrical schematics and PCB layouts to support characterization activities.
Troubleshoot signal integrity and electrical issues directly at probe points.
Investigate measurement anomalies and high-speed interface performance problems.
Apply practical electrical measurement and debugging techniques to identify potential issues.
Python Lab Automation
Develop and maintain
Python scripts
to automate laboratory measurements and characterization workflows.
Support repeatable and efficient execution of electrical tests.
Improve laboratory testing efficiency through reusable automation scripts.
Assist with measurement data collection, analysis, and documentation.
Cross-Functional Validation Support
Support high-speed interface validation activities across relevant silicon and systems platforms.
Collaborate with engineering teams to investigate electrical performance issues.
Communicate measurement findings, debugging results, and characterization progress.
Maintain clear technical documentation of test procedures, configurations, and results.
Required Qualifications
5+ years of experience
in post-silicon characterization, HSIO validation, or memory electrical validation.
Experience working at a semiconductor, silicon, or systems company in areas such as SoC, GPU, networking, storage, or automotive compute.
Hands-on experience with high-speed SerDes PHY characterization.
Practical experience measuring eye diagrams, jitter, BER, and S-parameters.
Proficiency using high-speed oscilloscopes, BERT, and VNA/TDR equipment.
Experience reading and interpreting schematics and PCB layouts.
Strong laboratory debugging and electrical measurement skills.
Python scripting experience for test and measurement automation.
Strong analytical, troubleshooting, and problem-solving abilities.
Willingness to work on-site in Palo Alto, CA.
Preferred Qualifications
Experience with
PCIe electrical characterization and validation
.
Exposure to Ethernet, UFS, or LPDDR5 interfaces.
Experience with high-speed signal integrity measurements and analysis.
Background in silicon validation for SoC, GPU, networking, storage, or automotive-compute products.
Experience developing reusable automation scripts and improving laboratory test efficiency.
Location: United States
Location:
Palo Alto, CA (On-site)
Job Type:
Contract
Job Overview
We are seeking an experienced
PCIe Characterization Engineer
to perform post-silicon electrical characterization and validation of high-speed SerDes PHYs. This role involves hands-on laboratory testing, electrical measurement, signal integrity analysis, and debugging of high-speed interfaces across PCIe, Ethernet, UFS, and LPDDR5 technologies.
The ideal candidate has a strong background in post-silicon characterization or high-speed I/O (HSIO) validation, with practical experience using advanced lab equipment and developing Python scripts for test automation.
Key Responsibilities
Perform post-silicon electrical characterization of high-speed SerDes PHYs and memory interfaces.
Conduct eye diagram, jitter, bit error rate (BER), and S-parameter measurements.
Operate high-speed oscilloscopes, bit error rate testers (BERT), vector network analyzers (VNA), and TDR equipment.
Analyze schematics and PCB layouts to identify signal integrity issues and support electrical debugging.
Perform hands-on troubleshooting and debug at the probe point to isolate and resolve hardware-level issues.
Develop and maintain Python scripts for laboratory test automation, data collection, and analysis.
Analyze characterization results, document findings, and collaborate with cross-functional engineering teams to improve interface performance.
Support validation activities for high-speed interfaces, including PCIe, Ethernet, UFS, and LPDDR5.
Required Qualifications
5+ years of experience in post-silicon characterization, HSIO validation, SerDes validation, or memory electrical validation.
Hands-on experience characterizing high-speed electrical interfaces in a semiconductor or systems engineering environment.
Proficiency with high-speed oscilloscopes, BERT, VNA, and/or TDR measurement equipment.
Practical experience measuring and analyzing eye diagrams, jitter, BER, and S-parameters.
Ability to read and interpret schematics and PCB layouts for hardware-level debugging.
Experience with Python scripting for laboratory automation and test data analysis.
Strong troubleshooting, analytical, and problem-solving skills.
Ability to work on-site in Palo Alto, California.
Preferred Qualifications
Experience with PCIe, Ethernet, UFS, LPDDR5, or other high-speed SerDes and memory interfaces.
Background working with SoCs, GPUs, networking hardware, storage systems, or automotive computing platforms.
Experience with signal integrity analysis and post-silicon hardware validation.
Previous experience in semiconductor, silicon design, or systems companies.
Ideal Candidate Profile
Candidates with titles such as
PCIe Characterization Engineer, Signal Integrity Engineer, HSIO Validation Engineer, Post-Silicon Validation Engineer, or SerDes Validation Engineer
are encouraged to apply.
Candidates currently based in the San Francisco Bay Area are strongly preferred due to the on-site nature of the position.
Location: Global, EU
We are the creators of a new fintech era!
Our mission is to change this world by making blockchain accessible to everyone in everyday life. WhiteBIT is a global team of over 1,200 professionals united by one mission — to shape the new world order in the Web3 era. Each of our employees is fully engaged in this transformative journey.
We work on our blockchain platform, providing maximum transparency and security for more than 8 million users worldwide. Our breakthrough solutions, incredible speed of adaptation to market challenges, and technological superiority are the strengths that take us beyond ordinary companies. Our official partners include the National Football Team of Ukraine, FC Barcelona, Lifecell, FACEIT and VISA.
The future of Web3 starts with you: join us as a !
Requirements
We're looking for a Senio/Staff-level engineer with an open mind and a builder's instinct - someone who goes beyond executing tasks and is ready to own the High-Performance practice end-to-end: establish engineering processes, drive R&D, evaluate and champion new technologies, and lead their adoption in production.
The ideal candidate can bridge the gap between business requirements for low latency and high throughput and the realities of existing infrastructure - translating "we need to be faster" into an actionable technical roadmap. You bring a fresh perspective, know how to organize the work, and are equally comfortable optimizing a hardware parameter and presenting a strategy to stakeholders.
We expect 5+ years of hands-on experience as a DevOps/SRE/Systems Engineer in performance-critical environments - and the maturity to grow yourself and grow a team around you.
Linux:
Advanced administration and OS-level tuning — real-time OS configurations, cgroups, CPU isolation, memory management, and low-level network stack configuration.
Hardware Internals:
Deep understanding of CPU power and performance states (C/P-states), Hyper-Threading / SMT trade-offs, TX/RX ring configuration, and the full data path from NIC through PCIe to memory and CPU. Ability to reason about and tune each stage of that path under production load.
Networking & TCP Internals:
Deep knowledge of TCP/IP — congestion control, ACK behavior, buffer tuning, and protocol-level latency sources. Strong Linux networking fundamentals: low-latency NIC configuration, bypass networking technologies (DPDK, RDMA), and market connectivity (multicast feeds, co-location networks, VPNs).
Performance Engineering:
Practical experience profiling latency-sensitive systems; familiarity with tools such as perf, flamegraph, strace, tcpdump, eBPF, and hardware performance counters.
Containerization:
Deep knowledge of Docker and Kubernetes, including low-overhead deployment patterns and performance trade-offs of containerized workloads.
IaC:
Proven track record with Ansible, Terraform, and Helm in production environments.
Monitoring:
Hands-on experience with the Prometheus / Grafana stack; ability to build latency-aware dashboards and alerting (P99, jitter, throughput KPIs).
Scripting:
Solid scripting in Bash and Python; Golang is a strong plus given its role in systems tooling.
CI/CD & Secret Management:
Strong grasp of CI/CD pipelines with experience integrating performance validation stages; familiarity with Vault for secrets management.
Security:
Understanding of DevSecOps principles and Kubernetes security policies.
Key Performance Metrics You'll Work With
Latency Distribution
- P99 / P99.9 across the tick-to-trade path, using hardware-level timestamps (NIC/PTP).
Jitter
- variance between min/max latency, measured over large sample sets in live market conditions.
Throughput
- messages per second (orders + cancels) under exchange burst scenarios.
System Reliability
- сontinuous monitoring of uptime
Extra Credit / Big Pluses
Hands-on experience with kernel-level optimization: syscall reduction, network stack bypass (DPDK, RDMA, Solarflare OpenOnload).
Background in HFT, algorithmic trading, or other ultra-low-latency production environments.
Experience with hardware timestamping, PTP/IEEE 1588, and precision time synchronization.
Familiarity with colocation operations and exchange connectivity (cross-connects, proximity hosting).
Proven SRE track record with formal SLO/error budget frameworks in latency-sensitive contexts.
DevSecOps: vulnerability scanning, Zero Trust, RBAC, and secure delivery pipelines.
Understanding of business processes in FinTech, crypto, or electronic trading.
Responsibilities
Low-Latency Infrastructure Ownership:
Design, deploy, and continuously optimize infrastructure for latency-sensitive trading systems — market data handlers, order/deal gateways, and risk check engines. Own the full stack from bare metal to application delivery. Define and maintain a reference architecture for low-latency connectivity when onboarding new trading venues, including reproducible configuration baselines, validation procedures, and performance acceptance criteria — so every new venue goes live on a proven, optimized stack.
Cloud & Hybrid Network Connectivity:
Design, implement, and maintain complex low-latency network solutions for cloud provider interconnects - including cross-connects and Direct Connect / ExpressRoute links between cloud regions, hybrid on-premise/cloud topologies, and high-throughput inter-server fabrics. Ensure both latency minimization and fault tolerance at every layer: physical redundancy, failover routing, and path diversity across providers and regions.
Hardware & OS Stack Tuning:
Go deep on the full hardware and OS stack - CPU pinning, C/P-states, HT/SMT configuration, NUMA topology, IRQ affinity, TX/RX ring sizing, NIC offloading, and network stack bypass (DPDK/RDMA where applicable). Understand the complete data path from NIC through PCIe to memory and CPU - and optimize every hop.
Infrastructure as Code (IaC):
Automate provisioning and configuration of high-performance environments using Ansible, Terraform, and Helm - with performance reproducibility as a first-class requirement.
Latency Profiling & Benchmarking:
Systematically profile and debug latency hotspots across the full execution path. Establish and maintain SLA/SLO targets; track P99/P99.9 distributions, jitter, and throughput - not just averages.
CI/CD for Performance:
Build and maintain CI/CD pipelines that include automated latency regression testing, so performance degradations are caught before they hit production.
Monitoring & Observability:
Design and operate comprehensive latency monitoring and alerting systems (Prometheus, VictoriaMetrics, Grafana) - including hardware timestamping (NIC/PTP) and fine-grained performance telemetry.
Colocation & Network Placement:
Research, evaluate, and manage optimal server placements - colocations, cross-connects, proximity hosting. Work closely with network and infrastructure teams to minimize physical and logical distance to exchanges.
High Availability & DRP:
Design systems that maintain stability and reliability under peak load while continuously pushing latency lower - zero regressions, always.
Cross-Team Collaboration:
Work alongside algo developers, quant teams, and network engineers to ensure trading strategies execute with minimal infrastructure overhead.
Working terms
Immerse yourself in Crypto & Web3:
Master cutting-edge technologies and become an expert in the most innovative industry.
Work with the Fintech of the Future:
Develop your skills in digital finance and shape the global market.
Take Your Professionalism to the Next Level:
Gain unique experience and be part of global transformations.
Drive Innovations:
Influence the industry and contribute to groundbreaking solutions.
Join a Strong Team:
Collaborate with top experts worldwide and grow alongside the best.
Work-Life Balance & Well-being:
Modern equipment.
Comfortable working conditions, and an inspiring environment to help you thrive.
24 calendar days of paid leave.
Additional days off for national holidays.
With us, you’ll dive into the world of unique blockchain technologies, reshape the crypto landscape, and become an innovator in your field. If you’re ready to take on challenges and join our dynamic team, apply now and start a new chapter in your career!
Let’s Build the Future Together!
WhiteBIT offers all candidates an equal opportunity to join the team. All hiring decisions are made without regard to race, national origin, gender identity or sexual orientation, age, religion, disability, medical condition, marital status, familial status, veteran status, or any other legally protected characteristic of an individual.
Проектирование архитектуры новых и развитие существующих продуктов линейки XPlatform как целостных программно-аппаратных решений. Определение оптимального состава аппаратного обеспечения (серверные платформы, системы хранения данных, сетевое оборудование, GPU) под требования производительности, масштабирования, отказоустойчивости и безопасности.
Проектирование и подбор серверных платформ под требования заказчика (производительность, надежность, бюджет). Сборка, модернизация и диагностика серверов (материнские платы, процессоры, память, охлаждение).
Nscale is looking for a Principal Technical Product Manager Hardware and AI Infrastructure to define and deliver scalable hardware infrastructure products.
Компания Vultr ищет опытного инженера по GPU, который будет заниматься проектированием, оптимизацией, проверкой и масштабированием GPU-инфраструктуры для задач искусственного интеллекта. В обязанности входит работа с технологиями PCIe, GPU, NCCL, а также обеспечение высокой производительности и надежности систем. Кандидат должен иметь опыт валидации, отладки и автоматизации процессов, включая использование Python и Ansible. Знание сетевых технологий, высокопроизводительных вычислений (HPC) и операционной системы Linux также требуется. Предлагается удаленная работа с конкурентной зарплатой в диапазоне от 190 000 до 210 000 долларов в год.
Location: US, Boston, MA
Workplace: OnSite
Here at Humanoid, we believe in a future where robots amplify human potential. That’s why we’ve set out on a mission to build the world’s most capable, commercially-scalable, and safe humanoid robots. We’re bringing that mission to life with HMND‑01 - our rapidly developed humanoid platform being deployed in real industrial environments - and we’re growing the team to take it even further.
ABOUT THE ROLE
As a Senior Electrical Engineer on the Hardware team in Boston, you’ll design and develop the electrical systems that bring advanced humanoid robots to life. This is a hands-on role where you’ll work across the full spectrum of robotics electrical engineering—from electrical system designs, electromechanical integrations, PCB layouts, firmware and device programming, to hands-on debugging in the lab. Your work will span from small test systems to fully integrated prototype robots, and provide you with a unique opportunity to have a big impact.
WHAT YOU’LL DO
- Design Electrical Systems for Robotics: Develop electrical systems that power and control Humanoid’s advanced robots, with a focus on sensors, compute architecture, and power systems.
- Conduct Circuit Analysis and Debugging: Use strong circuit analysis fundamentals to review electrical designs, conduct failure analysis, and troubleshoot complex electrical systems.
- PCB Design and Schematic Capture: Create detailed schematics and PCB layouts using Altium, ensuring the designs meet the performance, reliability, and manufacturability standards required for robotics.
- Develop Embedded Firmware: Write firmware in C and HDL to program microcontrollers, DSPs, and FPGAs, testing and refining embedded designs to ensure optimal performance.
- Leverage Linux for Robotics: Utilize your knowledge of command-line Linux to configure networks, run software, and interface with robots for testing and validation.
- Hands-On Lab Work: Use a variety of lab equipment, including oscilloscopes, DMMs, power supplies, programmable loads, and spectrum analyzers, to validate designs and solve complex electrical engineering challenges.
- Collaborate Across Teams: Work closely with mechanical engineers, software developers, and other team members to integrate electrical systems with robotics hardware, ensuring seamless operation and performance.
WHAT WE'RE LOOKING FOR
- Experience with high-speed data technologies such as PCIE, Ethernet, EtherCAT and/or other communication protocols in PCB-based devices and systems.
- Experience developing power regulation and distribution systems, including particular expertise with short-circuit protection systems, switching power supplies, and creative power management technologies.
- Proficiency with PCB design tools (e.g., Altium) for schematic capture and layout.
- Familiarity with embedded programming, including C, HDL, and other relevant languages for microcontrollers, DSPs, and FPGAs.
- Working knowledge of circuit simulation, analysis, and debugging techniques, including the use of oscilloscopes, power supplies, and spectrum analyzers.
- Experience with Python, C++, LabView, or MATLAB for automation and testing.
- Knowledge of SolidWorks or similar mechanical CAD tools.
- Familiarity with Verilog or VHDL for hardware design and simulation.
- Experience in building Linux kernels and modifying or writing device drivers.
Please note: few people will check every single box. If you’ve got solid electrical engineering fundamentals and strengths in some of these areas, we’d love to hear from you!
WHAT WE OFFER
- Comprehensive health coverage for US‑based employees, including fully paid medical, dental, and vision insurance, with virtual care and employee assistance resources.
- Generous time off to rest and recharge: 23 days of PTO (accrued), separate sick leave, and paid company holidays.
- 401(k) retirement plan with a 4% employer match.
- Meaningful equity with upside as we scale
- Free daily catered lunch, snacks, and drinks in‑office.
- Collaboration with top‑tier engineers, researchers, and product experts in AI and robotics.
- Freedom to influence the product and own key initiatives.
For this role in Massachusetts, the expected base salary range is $160K–$215K USD per year; your placement in that range depends on how your experience maps to our internal leveling.
Location: Israel; United Kingdom; France; Germany; Netherlands; Mexico
About us
At SPD Technology, we bring together a team of like-minded people who are driven by the desire to bring value through their work, united in their commitment to high performance and delivering custom, cutting-edge tech solutions that drive clients' growth. We empower our people with a culture of excellence, and enable them with the opportunity to uphold their accountability to contribute on each level. We value humanity and collaboration, encourage professional and personal growth, and foster a supportive and flexible work environment where everyone's contribution is welcomed.
We are looking for a Signal Integrity/Power Integrity Engineer to join us as part of our team.
About the role
As a Signal Integrity/Power Integrity Engineer you will work to shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology that powers the most demanding AI/ML applications. You will be part of a team developing custom silicon solutions, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production, while collaborating within a cross-functional team of Chip Design, IP, System Design, software, and vendors.
As a qualified expert You will
Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) leveraging advanced 2.5D/3D packaging technologies.
Partner early in product definition to influence chip floorplanning, power distribution networks (PDN/power trees), netlists, and routability tradeoffs.
Evaluate high-speed interface IPs and develop next-generation memory interfaces across IO PHY, SI/PI, and physical design boundaries.
Drive post-silicon validation and qualification for NPI, balancing SI/PI performance and DFM constraints to achieve final package design closure.
Partner closely with silicon, system, and external vendor teams while developing simulation methodologies to boost modeling accuracy and efficiency.
We're looking for you if you have
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in SI/PI design for chip/package or system PCB.
Experience in industry SIPI modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).
Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes.
Experience with partnering across chip architecture, physical design, static timing analysis (STA), package, and validation teams.
Experience in Python, MATLAB, or C++ to establish automated flows and data processing tools.
Bonus points
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Deep knowledge of SI/PI analysis for high-speed interconnects (HBMx, D2D/chiplets, PCIe, SerDes) and timing budget methodologies.
Direct experience with silicon interposers, silicon bridges, and 3D die stacking architectures.
What's in it for You
Reveal great tech solutions
Join the team of experts who create custom, cutting-edge tech solutions for world-renowned businesses, fueling clients growth. Unleash your potential, tackle new challenges, and be part of a team that values your skills and contributions. Focus on long-term impact and building tailored, long-lasting partnerships with our clients.
Experience an agile and flexible working environment
Work fully remote around the globe, or in a hybrid work model from our office hubs which are equipped with everything needed for comfortable work. Enjoy a flexible working schedule and create work and rest balance for yourself. Empower yourself with a stable workload and a stable income, focusing on lasting cooperation and high-performance culture.
Embrace the opportunity for personal and professional growth
Take advantage of performance review and career path. Elevate your skills with mentorship program, personal development plan, and individual learnings through the corporate library, public speaking support, and more.
Feel cared about
Be among like-minded people and feel supported with collaboration, open communication and mutual respect. Join company-wide tech and cultural events, and contribute to meaningful CSR initiatives that resonate with your values.
Interview steps
Interview with Recruiter
Manager Interview
Client Interview
Location: Torrance, United States
📍
Location:
Torrance, CA
📄
Employment Type:
Full-Time
🏢
Work Arrangement:
100% On-site, Monday–Friday
🚀
Start Date:
TBD
💰
Compensation:
TBD — based on skills and experience
Important Screening Requirements
Bachelor’s degree in
Electrical Engineering or a related field
.
Strong experience with complex
digital or mixed-signal hardware design
.
Experience with
high-speed digital systems, embedded processors, memory interfaces, and board-level architecture
.
Hands-on PCB design and hardware bring-up experience.
Experience using
oscilloscopes, logic analyzers, and power supplies
.
Experience with board validation, debugging, and root-cause analysis.
Must be able to work
on-site in Torrance, CA
.
U.S. work authorization and export-control eligibility requirements may apply.
Ability to obtain and maintain applicable U.S. Government security clearance or authorization, if required.
About the Role
We are seeking experienced
Avionics Hardware Engineers at the Senior and Staff levels
to work on high-speed digital design, flight computer architecture, and advanced avionics hardware.
This role is focused on complex embedded hardware for mission-critical systems, with ownership spanning
architecture, board design, bring-up, validation, and integration
.
What We’re Looking For
We’re looking for experienced hardware engineers who can take ownership of
complex avionics hardware
, solve challenging hardware problems in the lab, and work closely with multidisciplinary teams from architecture through integration.
Key Responsibilities
Design and develop advanced board-level electrical hardware, including:
Schematic capture
PCB layout oversight
Component selection
Interface definition
Own high-speed digital and embedded flight computer architectures involving processors, memory systems, and board-level integration.
Perform board bring-up, validation, debugging, and root-cause analysis in the lab.
Test reference boards and early prototypes using standard laboratory equipment.
Drive
signal integrity, power integrity, and hardware reliability
throughout the design lifecycle.
Collaborate with avionics, embedded software, test, and manufacturing teams.
Support hardware/software integration and troubleshooting across avionics platforms.
Document designs, test results, and engineering changes.
Required Qualifications
Bachelor’s degree in Electrical Engineering or related field.
Strong experience designing complex digital or mixed-signal hardware.
High-speed digital systems experience.
Experience with embedded processors, memory interfaces, and board-level architecture.
Experience with PCB design tools;
Altium preferred
.
Hands-on experience with oscilloscopes, logic analyzers, and power supplies.
Strong understanding of digital systems, signal integrity, power distribution, and hardware debugging.
Ability to work effectively in a fast-paced, highly collaborative environment.
Preferred Qualifications
Experience with
flight computer, avionics, or embedded compute architectures
.
Experience taking complex PCBAs from concept through bring-up, validation, and integration.
Exposure to embedded systems, firmware, or FPGA interaction.
Experience in aerospace, automotive, robotics, defense, or other high-reliability hardware environments.
Familiarity with
Ethernet, SPI, I2C, UART, CAN, PCIe, or DDR memory systems
.
Basic scripting or programming experience using
Python, C, or C++
.
Location: Torrance, United States
We are hiring experienced Avionics Hardware Engineers to specialize in high-speed digital design, flight computer architecture, and advanced avionics hardware development across our avionics organization. This role is ideal for engineers with deep EE fundamentals and hands-on ownership experience designing complex embedded hardware for mission-critical systems.
Engineers in this role focus on flight computer architecture, high-speed digital board design, system bring-up, and hardware validation across real flight hardware. The ideal candidate has experience owning complex board designs from architecture through integration and thrives in fast-paced hardware development environments.
RESPONSIBILITIES
Design and develop advanced board-level electrical hardware including schematic capture, PCB layout oversight, component selection, and interface definition.
Own high-speed digital and embedded flight computer architectures including processors, memory systems, and board-level integration
Perform board bring-up, validation, debugging, and root-cause analysis in the lab
Test reference boards and early prototypes using standard lab equipment
Drive signal integrity, power integrity, and hardware reliability considerations throughout the design lifecycle
Work with avionics, embedded software, test, and manufacturing teams to iterate designs quickly
Support hardware/software integration and troubleshooting across avionics platforms
Document designs, test results, and engineering changes clearly
BASIC QUALIFICATIONS
Bachelor's degree in electrical engineering or related field
Strong experience with complex digital or mixed-signal hardware design
Experience with high-speed digital systems, embedded processors, memory interfaces, and board-level architecture
Experience with PCB design tools (Altium preferred)
Hands-on experience with oscilloscopes, logic analyzers, and power supplies
Strong understanding of core EE principles including digital systems, signal integrity, power distribution, and hardware debugging
Comfortable working in a fast-paced, highly collaborative environment
PREFERRED QUALIFICATIONS
Experience owning flight computer, avionics, or embedded compute hardware architectures
Experience taking complex PCBAs from concept through bring-up, validation, and integration
Exposure to embedded systems, firmware, or FPGA interaction
Familiarity with aerospace, automotive, robotics, defense, or other high-reliability hardware environments
Familiarity with interfaces such as Ethernet, SPI, I2C, UART, CAN, PCIe, or DDR memory systems
Basic scripting or programming experience (Python, C/C++)
Location: United States
We are hiring experienced Avionics Hardware Engineers to specialize in high-speed digital design, flight computer architecture, and advanced avionics hardware development across our avionics organization. This role is ideal for engineers with deep EE fundamentals and hands-on ownership experience designing complex embedded hardware for mission-critical systems. Engineers in this role focus on flight computer architecture, high-speed digital board design, system bring-up, and hardware validation across real flight hardware. The ideal candidate has experience owning complex board designs from architecture through integration and thrives in fast-paced hardware development environments.
Responsibilities:
Design and develop advanced board-level electrical hardware including schematic capture, PCB layout oversight, component selection, and interface definition
Own high-speed digital and embedded flight computer architectures including processors, memory systems, and board-level integration
Perform board bring-up, validation, debugging, and root-cause analysis in the lab
Test reference boards and early prototypes using standard lab equipment
Drive signal integrity, power integrity, and hardware reliability considerations throughout the design lifecycle
Work with avionics, embedded software, test, and manufacturing teams to iterate designs quickly
Support hardware/software integration and troubleshooting across avionics platforms
Document designs, test results, and engineering changes clearly
Basic Qualifications:
Bachelor's degree in electrical engineering or related field
Strong experience with complex digital or mixed-signal hardware design
Experience with high-speed digital systems, embedded processors, memory interfaces, and board-level architecture
Experience with PCB design tools (Altium preferred)
Hands-on experience with oscilloscopes, logic analyzers, and power supplies
Strong understanding of core EE principles including digital systems, signal integrity, power distribution, and hardware debugging
Comfortable working in a fast-paced, highly collaborative environment
Preferred Qualifications:
Experience owning flight computer, avionics, or embedded compute hardware architectures
Experience taking complex PCBAs from concept through bring-up, validation, and integration
Exposure to embedded systems, firmware, or FPGA interaction
Familiarity with aerospace, automotive, robotics, defense, or other high-reliability hardware environments
Familiarity with interfaces such as Ethernet, SPI, I2C, UART, CAN, PCIe, or DDR memory systems
Basic scripting or programming experience (Python, C/C++
Location: Costa Mesa, United States
📍
Location:
Costa Mesa, California, USA
📄
Employment Type:
Full-Time
🏢
Work Arrangement:
On-site/Remote
🚀
Start Date:
Immediate
💰
Compensation:
TBD -- based on skills and experience
Important Screening Requirements
Must be a
U.S. Citizen or U.S. Permanent Resident (Green Card holder)
.
Must be eligible to obtain and maintain an
active U.S. Department of Defense (DoD) Secret Security Clearance
.
Candidates should have a strong interest in supporting advanced defense and national security programs.
About the Role
We are seeking an experienced
Senior Electrical Engineer, EMI/EMC Design
to lead EMI/EMC design, analysis, testing, and mitigation activities for advanced electrical and electronic systems. In this role, you will work across the product development lifecycle to identify and resolve electromagnetic compatibility challenges, support PCB and system-level design, and ensure compliance with applicable military and industry standards.
Key Responsibilities
Lead
EMI/EMC design, analysis, testing, and mitigation
activities for complex electrical systems.
Perform
Electromagnetic Environmental Effects (E3)
analysis and develop mitigation strategies.
Support specialized E3 areas including
HERO, HEMP, lightning protection, ESD, RF exposure limits, and operational electromagnetic compatibility
.
Plan and execute EMI/EMC testing using laboratory equipment such as spectrum analyzers, oscilloscopes, antennas, and LISNs.
Use simulation tools to analyze and troubleshoot EMI/EMC issues.
Review PCB layouts and electrical designs to ensure mechanical, electrical, EMI/EMC, and manufacturing requirements are met.
Read and interpret schematics and recommend appropriate design practices, grounding, filtering, and protection techniques.
Collaborate with electrical, mechanical, software, firmware, and systems engineering teams to resolve EMI/EMC issues.
Prepare technical reports, test documentation, and engineering recommendations.
Manage multiple engineering activities while meeting technical and schedule objectives.
Required Qualifications
Bachelor's degree in
Electrical Engineering, Electronics Engineering
, or a related field.
7+ years
of experience in
EMI/EMC design and testing
.
Familiarity with EMC/EMI standards and regulations, including:
MIL-STD-461G
MIL-STD-464D
RTCA DO-160
FCC
IEC
CISPR
SAE
Proven expertise in
E3 design, analysis, testing, and mitigation
.
Experience with
HERO, HEMP, lightning protection, ESD, RF exposure limits
, and operational electromagnetic compatibility.
Hands-on experience with EMI/EMC test equipment, including:
Spectrum analyzers
Oscilloscopes
Antennas
LISNs
Experience using simulation tools such as
ANSYS
and
CST Microwave Studio
for EMI/EMC analysis.
Strong understanding of
PCB layout techniques
, including multilayer design, grounding, filtering, and EMI/EMC considerations.
Ability to read and interpret electrical schematics.
Familiarity with interfaces such as
MIPI, DisplayPort, I2C, SPI, PCIe, and USB
.
Strong analytical, troubleshooting, communication, and organizational skills.
Preferred Qualifications
Experience supporting
aerospace, defense, or other high-reliability electronic systems
.
Experience leading EMI/EMC compliance activities from design through testing and qualification.
Experience with complex embedded electronic systems and mixed-signal PCB designs.
Strong understanding of electromagnetic compatibility considerations across system, PCB, and component levels.
Active
U.S. DoD Secret Security Clearance
.
