Вакансии

Ищем инженера, которому интересно работать на границе Software и Hardware. C/C++ → HLS → PS/PL → DMA → Linux Kernel → FPGA.

Созданием современных систем беспроводной связи с близкими к предельным характеристиками. Реализация алгоритмов приема и передачи физических стеков радиоинтерфейсов (ЦОС):

Компания Marvell ищет стажера-исследователя с уровнем PhD для работы в области FPGA и прототипирования на кремнии. Кандидат должен быть зачислен в программу PhD, MS by Research или MTech by Research по направлениям компьютерных наук, компьютерной инженерии, электроники, электротехники, робототехники или смежным дисциплинам.

Задачи: • Разработка и отладка RTL на Verilog • Разработка управляющего ПО на C (Microblaze, Vitis) • Интеграция P4-логики • Интеграция и настройка IP-ядер в Vivado • Реализация протоколов: 10G Ethernet, UDP, IPv4/IPv6, PTP (IEEE 1588), SyncE • Работа с интерфейсами: AXI4-MM / Stream / Lite • Интеграция 10G, DDR4, PCIe (XDMA), SPI, I2C • Оптимизация высокоскоростных трактов Требования: • Уверенный Verilog • Опыт разработки на C • Понимание архитектуры FPGA (Xilinx) • Опыт работы с Vivado / Vitis • Понимание Ethernet и UDP/IP • Опыт работы с AXI • Опыт интеграции 10G и PCIe Плюсом будет: • Опыт реализации PTP Transparent Clock (P2P / E2E) • Опыт работы с SyncE • Реализация WRED или других congestion control алгоритмов • Оптимизация high-speed datapath • Аппаратная обработка сетевого трафика Условия: • Официальное трудоустройство

Задачи: — Проектирование цифровых трактов для многоканальных когерентных систем: от захвата данных с высокоскоростных АЦП до формирования выходных потоков с жесткими требованиями к фазовой синхронизации между каналами. — Реализация конвейеров цифровой обработки сигналов в реальном времени: DDC, многоканальная фильтрация, спектральный анализ, формирование диаграммообразующих схем. — Разработка аппаратных блоков для пространственного анализа радиоэфира: обнаружение источников излучения, оценка их угловых координат, вычисление корреляционных матриц. — Участие в создании систем классификации сигналов: аппаратное ускорение вычисления признаков, корреляции с базами сигнатур, автоматическое определение типа и источника излучения. — Аппаратная реализация алгоритмов пеленгации и пространственной фильтрации (beamforming, адаптивные решетки, сверхразрешение). — Построение эффективных схем взаимодействия ПЛИС с процессорными системами (soft-процессоры, ARM-ядра SoC, внешние CPU) через высокоскоростные интерфейсы и DMA. — Работа с современными интерфейсами передачи данных от радиотрактов: JESD204B, LVDS. — Участие в формировании технического облика будущих продуктов: от выбора ПЛИС-платформы до распределения задач между логикой и софтом. Требования: — RTL-дизайн: профессиональное владение SystemVerilog, Verilog или VHDL. Понимание принципов конвейеризации, временных ограничений, ресурсной оптимизации. — Xilinx Vivado: уверенная работа со средой разработки, навыки аппаратной отладки (ILA, VIO), опыт работы с временными ограничениями (timing constraints). Опыт с ПЛИС 7-й серии и/или UltraScale+. — Скоростные интерфейсы: практический опыт настройки и отладки JESD204B (тактовой схемы, проблем детерминированной задержки и фазовой когерентности между линками). — Многоканальная ЦОС: понимание специфики синхронной обработки нескольких когерентных каналов в ПЛИС: фазовая синхронизация, параллельные конвейеры, межканальная калибровка. — Алгоритмы пространственной обработки: понимание принципов beamforming'а, корреляционной обработки, алгоритмов оценки углов прихода (Direction Finding), знакомство с методами сверхразрешения (MUSIC, ESPRIT и подобные). — Анализ и классификация: способность понять задачу вычисления признаков сигналов и их аппаратной классификации, эффективно реализовать корреляционные и спектральные метрики в ПЛИС. Будет плюсом: — Опыт реализации алгоритмов пеленгации (TDoA, интерферометрические методы, MUSIC) непосредственно в ПЛИС. — Понимание принципов адаптивных антенных решеток и методов подавления помех (null-steering, adaptive beamforming). — Опыт разработки под Zynq / Zynq UltraScale+ / RFSoC (PL + PS взаимодействие, Petalinux). — Опыт реализации автоматической классификации модуляции (AMC) или fingerprinting'а радиоизлучений. — Навыки моделирования алгоритмов пространственной обработки на Python или MATLAB перед переносом в ПЛИС. — Знакомство с SDR-экосистемой и практический опыт работы с микросхемами AD9361, ADRV9009 на уровне цифрового интерфейса. Условия: — R&D-задачи на переднем крае радиоэлектроники: от когерентного многоканального приема до интеллектуальной пространственной обработки. — Свободу в выборе алгоритмических и архитектурных решений, право голоса в технической стратегии. — Сильную команду, возможность расти в смежные области (HW, RF, системная архитектура). — Предоставление отладочного оборудования и референсных платформ. — Оформление по ТК РФ, гибкий график.

Location: Costa Mesa, United States ABOUT THE JOB We are looking for a FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA . You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification. This will require expertise in SystemVerilog, object-oriented programming, and UVM. If you are someone who has supported rapid avionics development, then this role is for you. WHAT YOU’LL DO Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs Develop verification plans with traceability to system and hardware requirements Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks Build functional coverage models and drive code coverage analysis to closure Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs Establish and maintain regression suites, tracking coverage metrics and verification progress Debug failures using waveform tools and simulation logs at the HDL and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement Support hardware validation and board bring-up on target platforms Ensure verification meets DO-254 and relevant safety standards Author verification closure reports and coverage analysis summaries REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 2+ years of experience in FPGA/ASIC verification Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches Object-oriented programming principles Industry simulators (Questa, VCS, Xcelium, or Vivado) Git-based collaborative workflows including code review Linux development environments Strong communication and teamwork skills Eligible to obtain and hold a U.S. Secret security clearance PREFERRED QUALIFICATIONS 5+ years of experience in FPGA/ASIC verification Master’s degree in Electrical Engineering, Computer Engineering, or related field DO-254, avionics verification standards for UAS, and safety-critical verification processes SVUnit or equivalent unit-testing frameworks Formal verification or CDC verification tools Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI Verification automation scripting (Python, Tcl, Makefile) SoC and ARM-based embedded platforms Verification automation, CI/CD integration, and Nix-based build environments

Location: Costa Mesa, United States WHAT YOU’LL DO Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs Develop verification plans with traceability to system and hardware requirements Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks Build functional coverage models and drive code coverage analysis to closure Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs Establish and maintain regression suites, tracking coverage metrics and verification progress Debug failures using waveform tools and simulation logs at the HDL and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement Support hardware validation and board bring-up on target platforms Ensure verification meets DO-254 and relevant safety standards Author verification closure reports and coverage analysis summaries REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 2+ years of experience in FPGA/ASIC verification Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches Object-oriented programming principles Industry simulators (Questa, VCS, Xcelium, or Vivado) Git-based collaborative workflows including code review Linux development environments Strong communication and teamwork skills Eligible to obtain and hold a U.S. Secret security clearance PREFERRED QUALIFICATIONS 5+ years of experience in FPGA/ASIC verification Master’s degree in Electrical Engineering, Computer Engineering, or related field DO-254, avionics verification standards for UAS, and safety-critical verification processes SVUnit or equivalent unit-testing frameworks Formal verification or CDC verification tools Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI Verification automation scripting (Python, Tcl, Makefile) SoC and ARM-based embedded platforms Verification automation, CI/CD integration, and Nix-based build environments

Location: Espoo Workplace: Hybrid ROLE HIGHLIGHTS: - Staff Engineer - Satellite Communications - Location: Espoo, Finland - Department: Fleet Control and Satellite Communications - Reports to: Director, Fleet Control and Satellite Communications - Employment type: Permanent - Workplace model: Hybrid. 3 days a week at the office - Employment is subject to applicable security screening (incl. SUPO, where required) WHY THIS ROLE MATTERS: As a Staff Engineer in Satellite Communications, you will own the satellite-to-ground link, the core communications protocols, and the end-to-end transmission of data from ground stations to customers. Trend is that our constellation produces an increasing volume of data and we want it down faster and more reliably. As we scale, the communications link sets the limit on what we deliver and how fast customers receive it. You'll own the end-to-end communication stack: the satellite-to-ground link (X-band, Ka-band and S-band), the underlying protocols used, and the transmission of data from ground stations to customers. Today these decisions are spread across several teams. This role brings them under one technical owner. The work sits where software meets physics. On one side are link budgets, modulation and coding, and spectrum constraints; on the other are schedulers, distributed systems and production operations. The hardest problems live where the two meet. You own what you build, from design to production, across a stack that combines cloud, on-prem and real hardware. Our engineering culture is AI-positive, with active use of copilots and LLMs to improve speed, code quality and productivity. WHO WE ARE ICEYE is the world leader in sovereign intelligence from space. We deliver persistent monitoring capabilities to detect and respond to changes in any location on Earth. ICEYE owns the world's largest and most advanced SAR (synthetic aperture radar) satellite constellation. To our customers we provide intelligence with unmatched quality, latency and revisit times, in any weather, day or night. To governments who choose to operate their own constellation we provide this proven capability as a sovereign system. ICEYE-built constellations serve customers in defence and intelligence, environmental monitoring, insurance and emergency management. We enable fast decisions that contribute to a safer future. Founded and headquartered in Finland, ICEYE operates globally with over 1000 employees across Europe, North America, the Middle East, and Asia-Pacific. YOUR DAY-TO-DAY RESPONSIBILITIES - Own the architecture of the satellite-to-ground link acrossX-band and Ka-band payload downlink and S-band command and control - Measure what the constellation delivers against its theoretical capacity, and lead the work that closes the gap - Design how data moves from ground station to customer, including latency tiers and delivery accounting - Build alongside software engineers, contributing code and reviews, not only architecture documents - Lead technical initiatives across team boundaries and align teams on link and data path decisions - Grow satellite communications expertise across the domain through mentoring, design reviews and shared standards WHAT WE'RE LOOKING FOR MUST HAVES: - Communications engineering on at least one flown mission, including personally diagnosing an anomaly on a live satellite. - High-rate payload downlink experience in X-band or Ka-band, beyond S-band command and control - Ability to build and defend a link budget: EIRP, G/T, Eb/N0, margin, rain fade, elevation constraints - Practical CCSDS knowledge: transfer frames, virtual channels, synchronisation and channel coding, file delivery - Experience owning how data moves from a ground station to where it is consumed, with latency and completeness guarantees - Hands-on coding in Python, Go, C++ or similar; you ship code, not just designs. NICE TO HAVES: - Active use of AI-assisted development tools (e.g., copilots, LLMs) to improve productivity, code quality, and problem-solving - Fleet-scale contact planning and scheduling across commercial ground station networks, especially leased third-party capacity - DVB-S2/S2X with adaptive coding and modulation - Delay-tolerant networking, or other store-and-forward file delivery with completeness accounting - SDR and DSP work: GNU Radio, FPGA or RFSoC, including personal or open-source projects - Awareness of spectrum regulation and coordination. We have a separate spectrum licensing team, so this is a plus rather than a requirement APPLICATION PROCESS - TA Partner Screen Call (30 min) - Hiring Manager Interview (90 min) - Technical Interview (120 min) - Values and Fit Interview (60 min) - Final interview with SVP of Engineering (60min) WORKING AT ICEYE At ICEYE, you'll join a diverse and highly engaged team united by the ambition to make the impossible possible. As a global scale-up, we combine speed and ambition with the opportunity to take real ownership from day one. Your growth, wellbeing, and success are a priority, with continuous professional development, training opportunities, and a culture where collaboration is how we win. HOW WE WORK (OUR VALUES) - Make the impossible possible: We set ambitious goals and stay calm under pressure. We bring grit, optimism, and ownership when things get hard, and we keep moving until we find a way. - Be curious: Go deep, ask questions, listen carefully, and think critically. Understand the “why” behind decisions. - See the big picture: Stay close to what's happening across the company so you can make better decisions. Consider how your work affects others. - Drive effective teamwork: Create psychological safety, invite different perspectives, and build inclusive teams. There are no bad questions. - Act as one team: We win together. We match tasks to the right owner and stay agile as priorities shift. - Have fun: What we do matters, and it should be enjoyable. Celebrate progress, take pride in results, and share the wins. BENEFITS Our benefits are designed to support your health and wellbeing, at work and beyond. We keep improving them based on employee feedback, and offerings vary by location. Talent Attraction will confirm what applies for this role and location during the process. OUR COMMITMENT TO DIVERSITY, EQUITY, AND INCLUSION We want ICEYE to be a place where people can be themselves and do great work. Different backgrounds and perspectives make us stronger, which is why we work to create an environment where people feel included, respected, and able to speak up. Whatever your background, we want you to bring your authentic self to the table. We're committed to fair, inclusive hiring and equal opportunity. Everyone is welcome to apply. If you need any adjustments or support during the recruitment process, tell us, and we'll do our best to help. Apply now to start your ICEYE journey, and help us continue to make the impossible possible together. Read more about ICEYE and working with us at iceye.com http://iceye.com.

Разработка встраиваемого программного обеспечения микроконтроллеров; Отладка и тестирование встраиваемого программного обеспечения.

Location: San Francisco, CA About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the RL teams Our Reinforcement Learning teams lead Anthropic's reinforcement learning research and development, playing a critical role in advancing our AI systems. We've contributed to all Claude models, with significant impacts on the autonomy and coding capabilities of Claude Fable 5.1 and Claude Opus 5.5. Our work spans several key areas: Developing systems that enable models to use computers effectively Advancing code generation through reinforcement learning Pioneering fundamental RL research for large language models Building scalable RL infrastructure and training methodologies Enhancing model reasoning capabilities We collaborate closely with Anthropic's alignment and frontier red teams to ensure our systems are both capable and safe. We partner with the applied production training team to bring research innovations into deployed models, and are dedicated to implementing our research at scale. Our Reinforcement Learning teams sit at the intersection of cutting-edge research and engineering excellence, with a deep commitment to building high-quality, scalable systems that push the boundaries of what AI can accomplish. About the role We're hiring for the Code RL team within the RL organization. As a Research Engineer, you'll advance our models' ability to design silicon. Hardware design is difficult and unforgiving – exactly the sort of domain we want Claude to excel at. You'll leverage your chip design expertise and turn it into tasks and signals for models to learn from. Specifically, you will: Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization. Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards. Conduct experiments and shape our roadmap. Deliver your work into research and production training runs. Collaborate with other researchers and engineers across and outside Anthropic. You may be a good fit if you: Have expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs. Are fluent with industry EDA tools and processes. Have taped out chips and have experience going from spec to silicon. Know how to balance research exploration with engineering implementation. Are passionate about AI's potential and committed to developing safe and beneficial systems. Strong candidates may also have: Experience with reinforcement learning, evaluations or environments. Built tooling or automation around chip design flows. Worked on ML accelerators or high-performance compute hardware. Familiarity with high-level synthesis or architecture simulators. The annual compensation range for this role is listed below. For sales roles, the range provided is the role’s On Target Earnings ("OTE") range, meaning that the range includes both the sales commissions/sales bonuses target and annual base salary for the role. Annual Salary: $500,000 — $850,000 USD Logistics Minimum education: Bachelor’s degree or an equivalent combination of education, training, and/or experience Required field of study: A field relevant to the role as demonstrated through coursework, training, or professional experience Minimum years of experience: Years of experience required will correlate with the internal job level requirements for the position Location-based hybrid policy: Currently, we expect all staff to be in one of our offices at least 25% of the time. However, some roles may require more time in our offices. Visa sponsorship: We do sponsor visas! However, we aren't able to successfully sponsor visas for every role and every candidate. But if we make you an offer, we will make every reasonable effort to get you a visa, and we retain an immigration lawyer to help with this. We encourage you to apply even if you do not believe you meet every single qualification. Not all strong candidates will meet every single qualification as listed.  Research shows that people who identify as being from underrepresented groups are more prone to experiencing imposter syndrome and doubting the strength of their candidacy, so we urge you not to exclude yourself prematurely and to submit an application if you're interested in this work. We think AI systems like the ones we're building have enormous social and ethical implications. We think this makes representation even more important, and we strive to include a range of diverse perspectives on our team. Your safety matters to us. To protect yourself from potential scams, remember that Anthropic recruiters only contact you from @anthropic.com email addresses. In some cases, we may partner with vetted recruiting agencies who will identify themselves as working on behalf of Anthropic. Be cautious of emails from other domains. Legitimate Anthropic recruiters will never ask for money, fees, or banking information before your first day. If you're ever unsure about a communication, don't click any links—visit anthropic.com/careers directly for confirmed position openings. How we're different We believe that the highest-impact AI research will be big science. At Anthropic we work as a single cohesive team on just a few large-scale research efforts. And we value impact — advancing our long-term goals of steerable, trustworthy AI — rather than work on smaller and more specific puzzles. We view AI research as an empirical science, which has as much in common with physics and biology as with traditional efforts in computer science. We're an extremely collaborative group, and we host frequent research discussions to ensure that we are pursuing the highest-impact work at any given time. As such, we greatly value communication skills. The easiest way to understand our research directions is to read our recent research. This research continues many of the directions our team worked on prior to Anthropic, including: GPT-3, Circuit-Based Interpretability, Multimodal Neurons, Scaling Laws, AI & Compute, Concrete Problems in AI Safety, and Learning from Human Preferences. Come work with us! Anthropic is a public benefit corporation headquartered in San Francisco. We offer competitive compensation and benefits, optional equity donation matching, generous vacation and parental leave, flexible working hours, and a lovely office space in which to collaborate with colleagues. Guidance on Candidates' AI Usage: Learn about our policy for using AI in our application process.

Location: Global, EU We are the creators of a new fintech era! Our mission is to change this world by making blockchain accessible to everyone in everyday life. WhiteBIT is a global team of over 1,200 professionals united by one mission — to shape the new world order in the Web3 era. Each of our employees is fully engaged in this transformative journey. We work on our blockchain platform, providing maximum transparency and security for more than 8 million users worldwide. Our breakthrough solutions, incredible speed of adaptation to market challenges, and technological superiority are the strengths that take us beyond ordinary companies. Our official partners include the National Football Team of Ukraine, FC Barcelona, Lifecell, FACEIT and VISA. The future of Web3 starts with you: join us as a Senior DevOps! Requirements We're looking for candidates with 5+ years of hands-on experience as a DevOps / SRE and deep expertise in the following technologies: Linux: Advanced administration and OS-level tuning — real-time kernels, process scheduling, memory management, cgroups, CPU isolation, and I/O optimization. Cloud platforms: Understanding of and experience in building complex systems focused on high availability (HA), low latency and high-performance computing (HPC) Networking: Deep understanding of TCP/IP, UDP, multicast, Ethernet, VLANs, and PTP at the wire level. Experience with low-latency network configurations and familiarity with kernel bypass technologies (DPDK, RDMA) is a strong plus. Containerization: Deep-dive knowledge of Docker and Kubernetes, including performance trade-offs of containerized workloads and low-overhead deployment patterns. IaC: Proven experience with Ansible, Terraform, and Helm in production environments. Hardware Performance: Working knowledge of how CPUs, NIC queues, memory, and storage behave under pressure. Hands-on experience with hardware tuning (BIOS configs, CPU isolation strategies, NIC queue management). Monitoring: Practical experience with the Prometheus / Grafana stack; ability to build latency-aware dashboards and fire meaningful alerts rather than noise. Scripting: Proven track record writing production scripts in Bash and Python. Golang is a significant plus. CI/CD: Strong grasp of core CI/CD tools and experience with secret management using Vault. Security: Understanding of DevSecOps principles and hands-on experience configuring security policies in Kubernetes (Zero Trust, RBAC, secure code delivery). Databases: Solid working knowledge of SQL and/or NoSQL databases under operational conditions. On-Call & Incident Response: High sense of ownership for production systems — willing to participate in on-call rotations and available to respond to critical incidents outside business hours when the situation demands. Extra Credit / Big Pluses Linux: Deep-dive into kernel-level optimization — from syscalls and network card tuning to DPDK or FPGA-based networking. Proven experience operating High Availability / Ultra-Low Latency solutions in live trading environments. Experience with hybrid infrastructures (on-premise + cloud) — colocations, cross-connects, and proximity hosting. Background in building and operating Big Data and Data Analytics platforms. Understanding of business processes in the FinTech / Banking / Crypto / HFT sector. Proven track record as an SRE with formal SLO / error budget frameworks. DevSecOps: Vulnerability detection, enforcing security best practices, and experience with scanning tools (Trivy or Snyk). Blockchain / crypto-native background is a bonus. Responsibilities Hybrid Infrastructure (Baremetal and Clouds): Administer Linux servers (Ubuntu, CentOS, RHEL), drive incident resolution, and take end-to-end ownership of system reliability. Low-Latency Systems Operations: Proactively monitor, troubleshoot, and tune latency-sensitive trading systems and exchange connections across multiple asset classes. You treat P99 latency as a first-class metric. OS & Hardware Tuning: Go deep on the Linux stack — CPU pinning, NUMA topology, IRQ affinity, kernel parameter tuning, NIC offloading, and BIOS-level configurations. If it affects the tick-to-trade path, you own it. Infrastructure as Code (IaC): Automate deployment and configuration using Ansible, Terraform, and Helm with performance reproducibility as a hard requirement. CI/CD: Build and maintain rock-solid CI/CD pipelines (GitLab CI, Jenkins, ArgoCD) including automated performance regression checks. Monitoring & Observability: Design and operate comprehensive monitoring and logging stacks (Prometheus, VictoriaMetrics, Grafana, ELK). Build latency-aware dashboards and alerting — P99/P99.9, jitter, throughput, and error rates. High Availability & DRP: Design and implement architectures adhering to HA, scalability, and Disaster Recovery principles — zero regressions while continuously reducing latency. Cross-Team Collaboration: Partner with quant, trading, and network engineering teams to squeeze every drop of performance from the full stack — from hardware up to application logic. Working terms Immerse yourself in Crypto & Web3: Master cutting-edge technologies and become an expert in the most innovative industry. Work with the Fintech of the Future: Develop your skills in digital finance and shape the global market. Take Your Professionalism to the Next Level: Gain unique experience and be part of global transformations. Drive Innovations: Influence the industry and contribute to groundbreaking solutions. Join a Strong Team: Collaborate with top experts worldwide and grow alongside the best. Work-Life Balance & Well-being: Modern equipment. Comfortable working conditions, and an inspiring environment to help you thrive. 24 calendar days of paid leave. Additional days off for national holidays. With us, you’ll dive into the world of unique blockchain technologies, reshape the crypto landscape, and become an innovator in your field. If you’re ready to take on challenges and join our dynamic team, apply now and start a new chapter in your career! Let’s Build the Future Together! WhiteBIT offers all candidates an equal opportunity to join the team. All hiring decisions are made without regard to race, national origin, gender identity or sexual orientation, age, religion, disability, medical condition, marital status, familial status, veteran status, or any other legally protected characteristic of an individual.

Location: Canada, Vancouver, BC Workplace: OnSite Here at Humanoid, we believe in a future where robots amplify human potential. That’s why we’ve set out on a mission to build the world’s most capable, commercially-scalable, and safe humanoid robots. We’re bringing that mission to life with HMND‑01 - our rapidly developed humanoid platform being deployed in real industrial environments - and we’re growing the team to take it even further. ABOUT THE ROLE We are looking for an Firmware and Embedded Software Engineer to design and develop the real-time software systems that control our humanoid robots. You will own the development of embedded software for critical robotic subsystems, including motion control, sensor interfaces, communication networks, and hardware abstraction layers that enable reliable and safe robotic operation. This role requires strong fundamentals in embedded programming, distributed hard real-time systems, and hardware-software integration, along with experience building robust software for complex electromechanical systems. You will collaborate closely with mechanical, electrical, and robotics engineers to rapidly prototype, test, and deploy embedded software that powers our robotic platforms. Your work will directly influence the performance, reliability, and responsiveness of Humanoid’s robots.   WHAT MAKES THIS ROLE EXCITING - Design and develop embedded systems that control humanoid robots in real time safely - Solve challenging problems in low-latency motion control, distributed embedded networks, and high-reliability robotic systems with various communication protocols - Work in a fast-moving hardware environment where software directly interacts with physical machines - Collaborate with a multidisciplinary robotics team spanning mechanical, electrical, controls, and AI - See your code deployed in real robots operating in real-world environments. WHAT YOU’LL DO - Develop and implement embedded software for robotic systems, emphasizing hard real-time performance and reliability as well as safety - Integrate and optimize hardware and software components, including sensors, actuators, and communication modules - Analyze and make recommendations on implementation paths with trade-offs - Write and debug firmware for microcontrollers, FPGAs, ASICs, and SoCs - Implement and manage communication protocols such as EtherCAT, CAN, UART, SPI, and I2C - Collaborate closely with mechanical and electrical engineers to ensure seamless system integration - Perform hardware testing, validation, and troubleshooting of embedded systems - Analyze system constraints and resource limitations to optimize performance and efficiency - Develop low-level drivers and interfaces for sensors, motors, and control electronics - Maintain clear documentation of system architecture, code, and test results for traceability and maintainability - Own embedded software components from concept through testing and deployment. WE’RE LOOKING FOR - 5+ years of professional experience developing embedded software or firmware for robotics, embedded systems, or real-time hardware platforms - Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, Robotics, or a related field - Strong proficiency in C and C++, with experience using Python for testing or tooling - Solid understanding of embedded systems architecture and hardware-software interfaces - Experience with real-time operating systems (RTOS) - Experience working with communication protocols such as EtherNet, EtherCAT, CAN, SPI, UART, or I2C - Experience integrating sensors, actuators, and motor control systems - Familiarity with debugging tools such as oscilloscopes, logic analyzers, and in-circuit debuggers - Strong analytical and problem-solving skills - Ability to work effectively in a fast-paced multidisciplinary engineering environment. BONUS QUALIFICATIONS - Experience working with robotics frameworks such as ROS or ROS2 - Hands-on experience with FPGA or SoC development - Experience developing distributed robotic control systems - Familiarity with agile development methodologies - Experience with EtherCAT-based motor drivers and real-time control networks - Experience developing safety-critical or high-reliability embedded systems.   WHAT WE OFFER - Comprehensive extended health benefits starting on your first day, including fully paid medical and dental, virtual care, employee and family assistance, and worldwide emergency medical support. - Meaningful time off to rest and recharge: 23 days of annual leave (accrued), 15 days of paid sick leave, and paid company holidays. - Paid end-of-year shutdown: annual company-wide holiday closure spanning Christmas through New Year’s Day. - Competitive equity: stock options with meaningful upside as we scale. - Free daily catered lunch, snacks, and drinks in‑office. - Collaboration with top‑tier engineers, researchers, and product experts in AI and robotics. - Freedom to influence the product and own key initiatives. For this role in Vancouver, the expected base salary range is $140,000 – $180,000 CAD per year; your placement in that range depends on how your experience maps to our internal leveling.

Задачи: — Функциональная верификация IP-блоков по полному маршруту с применением методологии UVM; — Отслеживание ошибок в проекте и взаимодействие с разработчиками; — Поддержка системы регрессионного тестирования / непрерывной интеграции; — Составление плана верификации. Требования: — Опыт в сфере верификации или разработки RTL для ASIC или FPGA от 3 лет (Verilog/ System Verilog, и т.п.); — Знание методологии UVM; — Знакомство с архитектурой современных процессоров, знание современных SoC интерфейсов (ACE, AXI, APB); — Знание System Verilog Assertion; — Уверенный пользователь ОС Linux; — Опыт использования системы контроля версий Git(GitLab); — Опыт в использовании VIP сторонних разработчиков; — Знание английского языка – на уровне чтения технической документации. Дополнительно приветствуется: — Владение скриптовыми языками (C, python, tcl, shell); — Опыт работы с системами непрерывной интеграции (Jenkins/Gitlab + Cadence Vmanager); — Опыт работы с внешними высокоскоростными физическими интерфейсами PCI-Express, DDR, ONFI/Toggle; — Навыки работы с PCI-Express и сетевыми интерфейсами (xxMII, SFI, SFP); — Навыки работы с продуктами Atlassian (Jira, Confluence). Условия: — Собственная R&D IT-лаборатория; — Официальное трудоустройство по ТК РФ; — Полный социальный пакет, включая ДМС; — График работы: гибридный; — Размер заработной платы: обсуждаем; — ИТ-аккредитация; — Бронь.

Location: United Kingdom; Colombia; Israel; Netherlands; France; Germany At SPD Technology, we bring together a team of like-minded people who are driven by the desire to bring value through their work, united in their commitment to high performance and delivering custom, cutting-edge tech solutions that drive clients’ growth. We empower our people with a culture of excellence and enable them with the opportunity to uphold their accountability to contribute on each level. We value humanity and collaboration, encourage professional and personal growth, and foster a supportive and flexible work environment where everyone’s contribution is welcomed. And now we are looking for a Senior Silicon System and Software Integration Engineer to join us as part of our team. About the role In this role, you will drive cutting-edge custom Machine Learning Accelerator (ASIC) technology that powers high-demanding, large-scale AI applications and global cloud infrastructure. You will leverage your design and verification expertise to evaluate complex digital designs, with a specific focus on ML compute architecture and its integration within AI/ML-driven systems. You will focus on ASIC development, validation, software, tools, and methodologies, pushing the boundaries of chip development and hardware-software integration. As a Senior Engineer, you will own cross-functional workstreams focused on end-to-end hardware-software integration and validation to demonstrate hardware, software, and system functionality and performance. You will serve as a key bridge between specification, design, and verification teams, as well as compiler and performance teams across the ML compute IP ecosystem. Work Environment Fully remote role. Flexible schedule with participation in team ceremonies and cross-functional collaboration. As a qualified expert, You will Review chip specifications and designs, developing integration plans with software and system partners while coordinating hardware/software delivery. Lead the bringup of ML compute features, integrating and validating complex hardware/software designs, including third-party IPs. Develop validation firmware to verify hardware functionality. Execute hardware-software co-simulation methodologies leveraging RTL, emulation, and field-programmable gate array (FPGA) environments. Utilize architectural simulators and performance models to correlate results. Design validation tests and microbenchmarks to verify IP functionality and performance. Author comprehensive test plans in coordination with cross-functional teams including Design, Design Verification (DV), Firmware, and Architecture. Own debug discussions with Design/DV/Software/Architecture teams and help root cause functional failures and performance issues throughout the product development cycle. Improve validation coverage and sign-off processes for high-quality tapeout and production deployment. We’re looking for you if you have Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience. 5 years of experience in two of the following: computer architecture, embedded firmware, ASIC design or verification, or the integration and enablement of first/third party IPs. Experience in hardware/software integration and validation. Experience with register-transfer level (RTL) development, design verification, and evaluation. Bonus Points Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 4 years of experience with C++/Python software design principles. Experience integrating complex hardware/software systems in accelerators. Experience developing firmware for embedded systems or accelerators. Experience in debugging firmware using simulation tools. Knowledge of real-time operating system (RTOS) internals. What’s in it for You Reveal great tech solutions Join the team of experts who create custom, cutting-edge tech solutions for world-renowned businesses, fueling clients growth. Unleash your potential, tackle new challenges, and be part of a team that values your skills and contributions. Focus on long-term impact and building tailored, long-lasting partnerships with our clients. Experience an agile and flexible working environment Work fully remote around the globe, or in a hybrid work model from our office hubs which are equipped with everything needed for comfortable work. Enjoy a flexible working schedule and create work and rest balance for yourself. Empower yourself with a stable workload and a stable income, focusing on lasting cooperation and high-performance culture. Embrace the opportunity for personal and professional growth Take advantage of performance review and career path. Elevate your skills with mentorship program, personal development plan, and individual learnings through the corporate library, public speaking support, and more. Feel cared about Be among like-minded people and feel supported with collaboration, open communication and mutual respect. Join company-wide tech and cultural events, and contribute to meaningful CSR initiatives that resonate with your values.

Requirements - Final year or Graduate student in Electrical/Computer Engineering or Communications.

Задача - разрабатывать DSP и PHY/MAC современных спутниковых и наземных цифровых модемов: MATLAB → C++ → FPGA/ARM/SoC → RF → готовое изделие.

Исправлением ошибок и разработкой новых функций в нашем варианте прошивки OpenBMC, в частности, с целью наладки взаимодействия с UEFI/BIOS x86. Взаимодействием с сообществом и мейнтейнерами проекта OpenBMC.

Location: Montreal, Canada 📍 Location: Montreal, Quebec, Canada 📄 Employment Type: Contract-to-Permanent (Preferred) / Contract 🏢 Work Arrangement: Remote Opportunity for US and Canadian citizens. Relocation allowance + bonus for European and UK Candidates. 🚀 Start Date: Immediate 💰 Compensation: TBD -- based on skills and experience Important Screening Requirements Must be legally eligible to work in Canada . Must be capable of obtaining the required security clearance . English proficiency is required. French is considered an asset. Strong hands-on experience with spacecraft Command & Data Handling (C&DH) systems is required. About the Role We are seeking an experienced Satellite Command & Data-Handling (C&DH) System Engineer to support the design, integration, verification, and operation of onboard command, control, and data-management functions for current and next-generation remote sensing and communications satellite programs. In this role, you will contribute to the C&DH functional architecture , drive technical trade studies, support system integration and verification, and provide technical leadership throughout the spacecraft lifecycle. Key Responsibilities Translate mission-level requirements into C&DH functional and non-functional requirements. Develop and maintain system requirements, Interface Control Documents (ICDs), and system descriptions. Maintain bidirectional requirements traceability throughout the project lifecycle. Support cybersecurity and resilience considerations within C&DH system design. Lead detailed design activities involving: Onboard processors Spacecraft data buses Memory subsystems I/O interfaces Support software architecture activities, including command sequencing, telemetry packetization, health monitoring, and FDIR. Support Satellite Reference Database development and validation. Define uplink command formats, downlink telemetry structures, and ground-segment data-handling interfaces. Collaborate with Flight Software (FSW), TT&C/PDT, and Ground Segment teams to ensure end-to-end data integrity. Develop verification plans, test matrices, and validation procedures for unit, subsystem, and spacecraft-level C&DH testing. Execute functional testing, bus-protocol compliance testing, and SIL/HIL campaigns. Lead anomaly investigations, root-cause analysis, and corrective-action activities. Support spacecraft launch preparation, early-orbit checkout, and on-orbit operations. Analyze on-orbit telemetry and support updates to operational parameters as required. Support SOOH development and operator training. Contribute to technical standards, process improvements, technology roadmaps, and engineering knowledge bases. Support major design reviews, including SRR, PDR, CDR, MRR, and TRR . Mentor junior engineers and serve as a technical liaison with customers, partners, and vendors. Required Qualifications Bachelor's degree in Electrical Engineering, Aerospace Engineering , or a related field. 8+ years of C&DH engineering experience on LEO, MEO, and/or GEO satellite platforms . Deep knowledge of spacecraft data-bus and communication standards, including: SpaceWire MIL-STD-1553 CAN Ethernet CCSDS packet telemetry and command PUS services Knowledge of processors, FPGA, firmware, and embedded systems . Strong understanding of aerospace systems engineering fundamentals, space environment, and orbit mechanics. Hands-on experience supporting systems integration, testing, troubleshooting, and problem resolution . Experience with Confluence and JIRA . Ability to work independently with minimal supervision. Strong analytical and problem-solving skills, with the ability to break down complex technical problems into fundamental components. Excellent written and verbal communication skills in English . Preferred Qualifications Experience supporting end-to-end spacecraft C&DH development and integration. Experience with spacecraft commissioning, early-orbit operations, and on-orbit telemetry analysis. Experience with FDIR , command sequencing, telemetry processing, and spacecraft health monitoring. Experience with SIL/HIL testing and spacecraft bus-protocol compliance verification. French language proficiency. Experience supporting satellite programs through the full lifecycle, from early concept and design through launch and on-orbit operations.