Вакансии

NVIDIA is hiring PCIE Verification Engineers with at least 1 year of experience.

Verify patient insurance benefits and eligibility. Review coverage, cost share, provider options, and restrictions.

Требования: — B.E/B.Tech/M.E/M.Tech в области электроники — Опыт работы в области верификации не менее 1 года

Cadence is looking to hire a Mixed-Signal Systems and Verification Engineer. The position is open to both experienced professionals and recent graduates. Candidates will be involved in tasks related to mixed-signal system design and verification processes. The role requires knowledge and skills in relevant engineering principles and verification methodologies. Applicants should be prepared to work on complex system-level challenges and contribute to the development and validation of mixed-signal technologies.

Требования: — Степень бакалавра в области электротехники, электротехнической и компьютерной инженерии, компьютерной инженерии или смежной области.

Location: El Salvador; Colombia; Nicaragua; Honduras; Ecuador; Guatemala We are seeking an energetic, outgoing, and exceptionally personable Bilingual Virtual Front Desk & Insurance Specialist to serve as the vital front-line ambassador for a fast-growing U.S.-based mental health practice. Combining high-volume inbound/outbound phone management, patient scheduling, and light insurance verification support, this is a highly patient-facing, high-touch role. We are specifically seeking a candidate with an upbeat, warm, confident, and engaging phone demeanor in both English and Spanish. Rather than a passive assistant, the practice requires a self-directed problem-solver who takes complete ownership of patient inquiries, manages heavy call volumes with ease, and provides an compassionate, outstanding experience for individuals seeking mental health and TMS therapy services. Working Environment & Core Schedule Role Title: Bilingual Front Desk & Insurance Verifications/Auths Specialist Status: Full-Time (40 Hours / Week) Schedule: Monday – Friday, 9:00 AM – 6:00 PM EST (US Eastern Standard Time) Language Requirement: Fully Bilingual (Fluent English & Spanish - Non-Negotiable) Practice Specialty: Psychiatry, Mental Health & TMS Therapy Top 3 Daily Tasks High-Volume Front Office Communication: Handle high-volume inbound and outbound patient calls (50–150 calls per day) using Weave, delivering exceptional customer care, answering treatment inquiries, and scheduling appointments. Patient Scheduling & Intake Management: Manage provider calendars, guide prospective mental health and TMS therapy patients through the intake process, and assist with general administrative requests. Insurance Verifications & Authorizations (Support): Provide occasional, targeted support with verifying insurance eligibility, checking benefit coverage, and navigating payer portals as needed. Core Responsibilities Inbound & Outbound Phone Operations: Serve as the primary voice of the practice using Weave, answering patient calls, conducting follow-up outreach, and managing appointment confirmations, cancellations, and reschedules in English and Spanish. Patient Inquiry & Care Coordination: Warmly address non-clinical questions regarding psychiatry, TMS therapy, and mental health services, guiding patients smoothly into the practice's care pipeline. Administrative Front Desk Support: Maintain accurate patient records, organize digital intake workflows, update patient charts, and manage daily calendar tasks using Google Workspace tools and GoHighLevel. Insurance & Auth Support: Perform secondary insurance eligibility checks, verify coverage details on payer platforms, and assist with prior authorization documentation when necessary. Proactive Problem-Solving: Identify administrative bottlenecks, manage high call density with composure, and maintain high patient satisfaction across every interaction. Requirements Bilingual Fluency: Fluent, natural spoken and written English and Spanish. U.S. Practice Experience: Minimum 2+ years of direct experience supporting a U.S.-based medical practice in a front-office, administrative, or patient-coordination capacity. Engaging Phone Demeanor: A bubbly, upbeat, warm, and highly confident phone presence—capable of building instant rapport without sounding scripted, timid, or robotic. Phone & Scheduling Proficiency: Proven background handling inbound/outbound calls, patient scheduling, and customer service. Lead & Growth Mindset: Comfort making outbound calls to prospective patients, addressing barriers to care, and guiding leads toward booking appointments. Problem-Solving Ability: Proven track record of working independently, following through on tasks without constant direction, and bringing solutions to operational challenges. HIPAA Compliance & Setup: Strong understanding of HIPAA guidelines and a quiet, private, HIPAA-compliant home workspace equipped with a high-speed computer setup and a clear noise-canceling headset. Strongly Preferred Lead Conversion & Sales: Background in patient acquisition, medical sales, or lead conversion. Specialty Practice Models: Direct experience in Direct Primary Care (DPC), Concierge Medicine, Medical Spa, Wellness, or Cash-Pay practice environments. Membership Billing: Hands-on experience with recurring membership billing models and membership CRM/lead management platforms. Ideal Candidate Profile You are a vibrant, articulate, and resourceful bilingual coordinator who loves connecting with people over the phone. You treat every patient and prospective lead like a VIP, take immense pride in keeping clinic workflows organized, and take full ownership of helping a medical practice grow.

Требования: — Завершённое образование BE/BTech в области ECE или смежной области (обязательно). — Свежие выпускники 2025 или 2026 года.

Требования: — 3-5 лет опыта работы в области ASIC Verification Engineering.

Требуется инженер по верификации дизайна SoC с опытом работы от 2 до 4 лет.

Location: Brazil; Peru; Sweden; Colombia; Argentina; Romania; Malta; Slovenia; Lithuania; Czech Republic; Estonia; Hungary; Mexico; Chile; Poland; Bulgaria Workplace: Remote BUILDING THE FUTURE OF OPEN FINANCE Payward - the parent company behind Kraken, NinjaTrader, Breakout, xStocks, Payward Services and CF Benchmarks - has spent the last 15 years building one of the most modern and globally accessible financial infrastructure platforms in the industry, built to advance an open, global financial system. THE TEAM Founded in 2011, Kraken is one of the world's longest-standing crypto platforms, trusted by over 10 million individuals and institutions across the globe. It offers spot trading, margin, futures, staking, and OTC services, with products built for both individual investors and institutional clients. The Pro Verifications team decides whether a business signing up on the Pro side is who it says it is, and whether we're allowed to onboard it. That means figuring out who actually owns the business, running it against sanctions and watchlists, and doing all of it fast enough that a real customer doesn't lose patience and leave. Every Pro customer hits these systems, so slow or wrong is very visible — and the team is early, which means whoever joins gets to decide how a lot of it works instead of inheriting it. How We Work - We deploy constantly, almost always behind a flag, in pieces small enough to pull back fast. - Security and compliance show up at design time, not as a gate at the end. - Every story is tied to a metric it's meant to move — if work isn't on the board, it doesn't get staffed. - At this level, you're expected to shape these standards, not just work inside them.   THE OPPORTUNITY As a Staff Engineer on Pro Verifications, you'll own the technical direction for how verification is built here — the architecture, the patterns other engineers work inside, and the calls about what we own versus what we lean on a vendor for. You'll be hands-on across the stack, drive out entire classes of recurring failure rather than patching them one at a time, and design the fail-closed and audit behavior that keeps regulators satisfied. This is a high-impact, hands-on technical leadership role for engineers who've built where being wrong has real consequences, and who want to shape a system that stays fast, safe, and defensible as it grows. - Set the shape of the verification services and their contracts across the KYC/KYB flow. - Decide how we abstract KYC and KYB vendors so a bad provider day doesn't turn into an outage. - Design fail-closed behavior and audit trails that hold up under regulatory scrutiny. - Identify the classes of failure that keep recurring and remove them for good. - Write and drive architecture decisions (ADRs), and hold the line on security and compliance at design time, not as a late gate. - Mentor and raise the bar for senior engineers through design reviews, code, and direct feedback. - Be measured on whether verification gets faster, more of it decides itself, fewer decisions are wrong, and the systems stay up — and on whether the team got stronger for you being on it.   WHAT YOU BRING - Around eight years building and running production systems, with a track record of owning a domain's technical direction, not just delivering inside one. - Deep, fluent expertise in Rust, with the versatility to work across TypeScript and React where verification meets the customer. - You've set architecture other people build on, and it held up — you can point to specific classes of failure you designed out, not just incidents you fixed. - You've made teams faster through patterns, tooling, or mentoring — engineers around you got better and shipped more because of calls you made. - You've built where being wrong had real consequences: compliance, payments, security, or anywhere a bad call costs more than a rough user experience. - Strong on distributed systems, service contracts, and secure design — you've integrated third-party APIs that couldn't be trusted, with real timeouts, retries, idempotency, circuit breakers, and backup paths that actually get tested. - Comfortable with, or able to quickly ramp on, gRPC, Temporal, Docker, Kubernetes, Terraform, MySQL/MariaDB, Redis, and GitLab CI.   NICE TO HAVES - Direct experience with KYC, KYB, or fraud work, including integrating providers like Trulioo, Persona, or ComplyAdvantage. - Comfort building with AI in the loop. - Time spent in crypto, fintech, or another space regulators pay close attention to.         Unless a specific application deadline is stated in the job posting, applications are accepted on an ongoing basis. Please note, applicants are permitted to redact or remove information on their resume that identifies age, date of birth, or dates of attendance at or graduation from an educational institution. We consider qualified applicants with criminal histories for employment on our team, assessing candidates in a manner consistent with the requirements of the San Francisco Fair Chance Ordinance. OUR COMMITMENT Payward is powered by people from around the world and we celebrate the diverse talents, backgrounds, contributions, and unique perspectives that everyone brings to the table. We hire based on merit, seeking out people with the right abilities, knowledge, and skills for the job. We encourage you to apply for roles where you don't fully meet the listed requirements, especially if you're passionate or knowledgeable about crypto. We may ask candidates to complete job-related skills or work-style assessments as part of our hiring process. These assessments evaluate competencies relevant to the role and are applied consistently across candidates for similar positions. Results are considered alongside experience and interviews, and are not the sole basis for any employment decision. As an equal opportunity employer, we don't tolerate discrimination or harassment of any kind, whether based on race, ethnicity, age, gender identity, citizenship, religion, sexual orientation, disability, pregnancy, veteran status, or any other protected characteristic as outlined by federal, state, or local laws. Stay connected Follow us on Twitter https://twitter.com/krakenfx Learn on the Kraken Blog https://blog.kraken.com/#:~:text=Enter%20your%20email%20address Connect on LinkedIn https://www.linkedin.com/company/kraken-exchange/ Candidate Privacy Notice https://www.kraken.com/legal/candidate-privacy-notice

Location: Montreal, Canada ON-SITE IN MONTREAL IS PREFERRED; REMOTE OR HYBRID IS POSSIBLE FOR THE RIGHT CANDIDATE. * OPEN TO US AND EUROPE BASED CANDIDATES * The selected candidate will contribute to the entire payload lifecycle — from architecture definition and requirement specification to integration, verification, and in-orbit validation. The role requires good understanding of both digital signal processing and RF payload architectures, especially involving Software Defined Radio (SDR) and Direct Radiating Array (DRA) systems. TASK • Define, analyze, and validate system and subsystem requirements for digital telecommunications payloads. • Develop and execute verification plans, including defining test strategies, writing test procedures, and analyzing results. • Lead or support system-level payload test campaigns, both at equipment and spacecraft level. • Interface with payload hardware and software teams to ensure correct implementation and traceability of requirements. • Participate in technical reviews and support anomaly investigation and resolution. • Work with multi-disciplinary teams including RF, digital, embedded software, FPGA, and systems engineering. • Contribute to technology evolution by identifying opportunities for design optimization and innovation. MUST HAVE • Bachelor’s degree in Electrical Engineering, Telecommunications, Aerospace Engineering, or a related field. • 5 years+ of experience in telecommunications systems, particularly in digital payloads. (experience outside of the Space industry will also be considered) • Strong expertise in requirements verification by test, including practical experience in developing and executing test plans. • Solid understanding of digital payload architectures, including SDR-based flexible processors and beamforming using DRA. • Familiarity with hardware and software tools used in payload verification, such as: Vector Network Analyzers (VNA) and Spectrum Analyzers for RF testing, Baseband signal generators, Channel Emulators, and BER testers, Python, MATLAB, or LabVIEW for test automation and data analysis, SCPI, VISA, and similar interfaces for instrument control • Good understanding of FPGA-based systems and embedded software architectures is a plus. • Must be eligible to work in Canada, capable of obtaining necessary security clearance. COMPLIMENTARY SKILLS/KNOWLEDGE • Previous experience in Space or Constellation Operations • Development and testing of new automated testing methodologies • Knowledge of requirements Management tools such as DOORS/Windchill/Jama • Demonstrated capability to efficiently work autonomously and with little to no supervision • Written and verbal communications skills in English, knowledge of French will be considered favorably

Location: Espoo Workplace: OnSite Role highlights: - Location: Espoo, Finland - Department: Global Manufacturing Organization - Reports to: Manager, Logistics Management - Employment type: Permanent - Workplace model: On-site (Cleanroom) - Employment is subject to applicable security screening (incl. SUPO, where required) Why this role matters: As an Electronics Verification Technician, you are a critical part of the highly international manufacturing team specifically responsible for ensuring every PCBA functions flawlessly before assembly. Reporting to the Electronics Verification Team Lead, embedded within the Logistics and QC Department, you will work in a clean area with ESD sensitive devices and classified information, operating test stations, high precision equipment, verifying electronic board assemblies, performing visual inspections, troubleshooting failed tests and providing immediate feedback to prevent defects from moving down the assembly line. Who We Are ICEYE is the world leader in sovereign intelligence from space. We deliver persistent monitoring capabilities to detect and respond to changes in any location on Earth. ICEYE owns the world's largest and most advanced SAR (synthetic aperture radar) satellite constellation. To our customers we provide intelligence with unmatched quality, latency and revisit times, in any weather, day or night. To governments who choose to operate their own constellation we provide this proven capability as a sovereign system. ICEYE-built constellations serve customers in defence and intelligence, environmental monitoring, insurance and emergency management. We enable fast decisions that contribute to a safer future. Founded and headquartered in Finland, ICEYE operates globally with over 1,000 employees across Poland, Spain, Germany, the UK, Australia, Japan, the UAE, Greece, and the US. Read more about our latest financial results and growth https://www.iceye.com/newsroom/press-releases/scaling-sovereign-intelligence-from-space-iceye-announces-2025-financials-250m-revenue-100m-profitability-and-1.5b-backlog?hs_preview=VihREVTI-209111858013&hsLang=en. Your day-to-day responsibilities - Conduct visual inspections, electrical verifications, and basic mechanical tests as well as quality checks during incoming operations of electronic parts, mechanical parts, commercial off-the-shelf (COTS) items, and subsystems to ensure compliance with specifications; - Update material status in the ERP and MES system, Record inspection results and maintain accurate, audit-ready, documentation; - Report non-conformances, support root cause analysis activities, contribute to the implementation of corrective and preventive actions across production and the supply chain, communicate persistent assembly errors to the production lead; - Perform real-time visual and mechanical inspection of SMT and Through-Hole assemblies to IPC-A-610 and J-STD-001 standards. - Flash firmware and bootloaders onto microcontrollers, troubleshoot test failures in real-time, identifying whether the issue is a component failure, soldering defect, or test fixture error. - Occasionally perform minor rework on non-conforming boards to keep production flowing. - Ensure inspection tools and equipment are properly calibrated and maintained; - Monitor inspection, logistics, production, storage, and laboratory environments to ensure compliance with safety and quality standards to support consistent manufacturing operations. What we’re looking for Must haves: - Strong background in Electronics, Mechatronics, Testing, or related fields, with computer literacy in Jira, Confluence, MES Systems, Linux, and with programming knowledge in Python, CSV, Bash, etc. - Direct hands-on experience in the use of complex electronic measurement tools, oscilloscopes, multimeters, bench power supplies, VNA, test jigs, etc. - Conversational level of spoken and written English. - Degree, diploma or applicable certifications: Master of Science in Engineering (MSc) recently graduated, Engineer, Advanced university student, Bachelor with a minimum of 2 years of experience in similar environments, or 5 years of proven enthusiastic experience, IPC-A-600, IPC-A-610, J-STD-001, ESA/ECSS. - Experience with basic hand-soldering rework tools. - Ability to coach peers constructively on the production floor. Nice to haves: - Knowledge of industrial practices, non-conformance reporting, root cause analysis, calibration requirements, ESD, manufacturing workflows, . - Strong ability to read PCB assembly drawings, Bill of Materials (BOMs), schematics and trace circuits to find shorts or open connections and defect recognition (polarity, bridging, cold joints, missing components). - Experience in mechanical inspection of individual parts and assemblies. - Exposure to Assembly, Integration and Tests environments of Satellite Hardware. Application Process - Recruiter call - Hiring Manager interview - Technical task - Team interview - Final interview Working at ICEYE At ICEYE, you’ll join a diverse and highly engaged team united by the ambition to make the impossible possible. As a global scale-up, we combine speed and ambition with the opportunity to take real ownership from day one. Your growth, wellbeing, and success are a priority, with continuous professional development, training opportunities, and a culture where collaboration is how we win. How We Work (Our Values) Make the impossible possible: We set ambitious goals and stay calm under pressure. We bring grit, optimism, and ownership when things get hard, and we keep moving until we find a way. - Be curious: Go deep, ask questions, listen carefully, and think critically. Understand the why behind decisions. - See the big picture: Stay close to what’s happening across the company so you can make better decisions. Consider how your work affects others. - Drive effective teamwork: Create psychological safety, invite different perspectives, and build inclusive teams. There are no bad questions. - Act as one team: We win together. We match tasks to the right owner and stay agile as priorities shift. - Have fun: What we do matters and it should be enjoyable. Celebrate progress, take pride in results, and share the wins. Benefits Our benefits are designed to support your health and wellbeing, at work and beyond. We keep improving them based on employee feedback, and offerings vary by location. Talent Acquisition will confirm what applies for this role and location during the process. Our Commitment to Diversity, Equity, and Inclusion We want ICEYE to be a place where people can be themselves and do great work. Different backgrounds and perspectives make us stronger, which is why we work to create an environment where people feel included, respected, and able to speak up. Whatever your background, we want you to bring your authentic self to the table. We’re committed to fair, inclusive hiring and equal opportunity. Everyone is welcome to apply. If you need any adjustments or support during the recruitment process, tell us and we will do our best to help. Apply now to start your ICEYE journey and help us continue to make the impossible possible together. Read more about ICEYE and work with us at iceye.com http://iceye.com.

Location: Montreal, Canada The Satellite-Level Verification and Validation (V&V) Engineer focuses on the highest tier of spacecraft integration, ensuring the fully assembled satellite meets all mission, launch provider, and environmental requirements. Role Overview This role manages the end-to-end verification lifecycle at the highest tier of architecture. It starts at the beginning of the program with verification planning and test methodology design, continues through full-system functional and environmental validation, and concludes with final qualification sign-off and in-orbit initialization readiness. Key Responsibilities & Tasks Verification Architecture & Matrix Ownership: Define the global verification strategy; author the System Verification Plan (SVP) and own the master Verification Control Matrix (VCM) to prove 100% requirement compliance. Method of Compliance (MoC) Definition: Determine the optimal, most cost-effective blend of Verification by Test, Analysis, Demonstration, and Inspection (TADI) for complex mission-level requirements. End-to-End Mission Validation: Design and execute full-system functional tests, "Day-in-the-Life" (DITL) mission simulations, and complex Fault Detection, Isolation, and Recovery (FDIR) validation scenarios. Environmental & Launch Qualification: Define test profiles, pass/fail criteria, and post-test correlation frameworks for full spacecraft environmental campaigns (Thermal Vacuum, Sine-Vibe, Acoustic, Shock). Sign-off & Qualification Review: Lead Technical Review Boards, manage non-conformance reports (NCRs), present compliance evidence at Qualification Reviews (QR), and build the final Flight Readiness data package. Candidate Prerequisites ("Must Haves") Experience: 5+ years in aerospace systems engineering, systems V&V, or space mission qualification roles. Systems Engineering Mastery: Deep understanding of how platform subsystems and digital/RF payloads interact to satisfy top-level mission performance metrics. Requirements Management: Expert-level capability in tracing, decomposing, and closing out complex requirements using enterprise tools like DOORS, Jama, or Windchill. Data Synthesis & Analysis: Advanced skills using Python or MATLAB to parse multi-subsystem telemetry, correlate test data with analytical models, and automate post-test verification reporting.

Location: Montreal, Canada The Platform Systems Verification and Validation (V&V) Engineer focuses on the satellite bus , ensuring the core infrastructure subsystems are fully verified and ready to support the payload. Role Overview This role focuses on the functional verification of the utility subsystems that keep the satellite alive and oriented. It ensures the core platform—including power, thermal control, propulsion, and pointing—operates flawlessly and responds correctly to the onboard flight software. Key Responsibilities & Tasks Bus Subsystem Verification : Test and validate critical platform subsystems, including Attitude Determination and Control (ADCS), Electrical Power Subsystems (EPS), Thermal Control (TCS), and Propulsion. Hardware-in-the-Loop (HIL) : Utilize HIL testbeds to simulate orbital dynamics and sensor inputs (star trackers, GPS, sun sensors) to verify ADCS pointing accuracy. Power & Harness Validation : Perform power budget verification, battery charge/discharge cycle testing, and solar array simulator (SAS) integration. Flight Software (FSW) Interfacing : Test command routing, telemetry packet generation, and fault detection, isolation, and recovery (FDIR) loops. Subsystem Interface Control : Verify that all physical, data (CAN, SpaceWire, RS-422), and electrical interfaces between platform subsystems are compliant. Candidate Prerequisites ("Must Haves") Experience : 5+ years verifying aerospace subsystems, embedded robotics, or satellite platform architectures. Technical Breadth : Strong knowledge of power electronics, orbital mechanics, thermal management, or control systems. Simulators & Automation : Experience with automated test scripting (Python/MATLAB) to control power supplies, loads, and simulated sensor inputs. Protocol Expertise : Familiarity with space-industry data protocols and avionics testing architectures.

Location: Costa Mesa, United States ABOUT THE JOB We are looking for a FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA . You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification. This will require expertise in SystemVerilog, object-oriented programming, and UVM. If you are someone who has supported rapid avionics development, then this role is for you. WHAT YOU’LL DO Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs Develop verification plans with traceability to system and hardware requirements Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks Build functional coverage models and drive code coverage analysis to closure Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs Establish and maintain regression suites, tracking coverage metrics and verification progress Debug failures using waveform tools and simulation logs at the HDL and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement Support hardware validation and board bring-up on target platforms Ensure verification meets DO-254 and relevant safety standards Author verification closure reports and coverage analysis summaries REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 2+ years of experience in FPGA/ASIC verification Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches Object-oriented programming principles Industry simulators (Questa, VCS, Xcelium, or Vivado) Git-based collaborative workflows including code review Linux development environments Strong communication and teamwork skills Eligible to obtain and hold a U.S. Secret security clearance PREFERRED QUALIFICATIONS 5+ years of experience in FPGA/ASIC verification Master’s degree in Electrical Engineering, Computer Engineering, or related field DO-254, avionics verification standards for UAS, and safety-critical verification processes SVUnit or equivalent unit-testing frameworks Formal verification or CDC verification tools Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI Verification automation scripting (Python, Tcl, Makefile) SoC and ARM-based embedded platforms Verification automation, CI/CD integration, and Nix-based build environments

Location: Costa Mesa, United States WHAT YOU’LL DO Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs Develop verification plans with traceability to system and hardware requirements Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks Build functional coverage models and drive code coverage analysis to closure Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs Establish and maintain regression suites, tracking coverage metrics and verification progress Debug failures using waveform tools and simulation logs at the HDL and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement Support hardware validation and board bring-up on target platforms Ensure verification meets DO-254 and relevant safety standards Author verification closure reports and coverage analysis summaries REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 2+ years of experience in FPGA/ASIC verification Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches Object-oriented programming principles Industry simulators (Questa, VCS, Xcelium, or Vivado) Git-based collaborative workflows including code review Linux development environments Strong communication and teamwork skills Eligible to obtain and hold a U.S. Secret security clearance PREFERRED QUALIFICATIONS 5+ years of experience in FPGA/ASIC verification Master’s degree in Electrical Engineering, Computer Engineering, or related field DO-254, avionics verification standards for UAS, and safety-critical verification processes SVUnit or equivalent unit-testing frameworks Formal verification or CDC verification tools Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI Verification automation scripting (Python, Tcl, Makefile) SoC and ARM-based embedded platforms Verification automation, CI/CD integration, and Nix-based build environments

Location: Barcelona, Spain; Budapest, Hungary; Düsseldorf, Germany; Frankfurt, Germany; Krakow, Poland; Krosno, Poland; Liège, Belgium; Lille, France; Vilnius, Lithuania; Ljubljana, Slovenia; Lublin, Poland; Lyon, France; Madrid, Spain; Città Vittoriosa, Malta; Podgorica, Montenegro; Poland; Sarajevo, Bosnia and Herzegovina; Banská Bystrica, Slovakia; Sofia, Bulgaria; Stuttgart, Germany; Tenerife, Spain; Wien, Austria; Warsaw, Poland; Zagreb, Croatia; Zürich, Switzerland; Petten, Netherlands; Aachen, Germany; Athens, Greece; Augsburg, Germany; Bad Homburg, Germany; Baden-Baden, Germany; Berlin, Germany; Bolzano, Italy; Bordeaux, France; Bratislava, Slovakia; Bromolla, Sweden; Brussels, Belgium; Bucuresti, Romania; Bucharest, Romania; Buenos Aires, Argentina; Dusseldorf, Germany; Hamburg, Germany; Hannover, Germany; Luxembourg; Amsterdam, Netherlands; Pondicherry, India; Ahmedabad, India; Berat, Albania; Delhi, India; Dnipro, Ukraine; Helsinki, Finland; Bangalore, India Workplace: remote At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Senior Formal Verification (FV) Engineer to join one of our clients' teams. Reporting directly to the Vector Unit Verification Lead, this is a highly technical Individual Contributor (IC) role. In this position, you will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. You will work side-by-side with VU microarchitects to hunt down deep corner-case bugs and achieve formal sign-off on high-complexity arithmetic and execution blocks. Key Responsibilities Block-Level Execution & Convergence Engineering (90%) End-to-End Testbench Ownership: Design, deploy, and maintain robust formal verification environments for complex Vector Unit sub-blocks (e.g., Vector Execution Pipelines, Vector Register File/Rename interfaces, and Vector Floating-Point Units). Datapath & Arithmetic Verification: Implement advanced word-level modeling, bit-blasting, and algebraic rewriting strategies to verify complex IEEE-754 floating-point and integer vector arithmetic units. Proof Convergence Management: Independently diagnose and resolve proof-convergence failures, over-constraints, and state-space explosions using advanced reduction techniques (e.g., case-splitting, black-boxing, and abstraction modeling). RISC-V Vector Compliance: Develop formal environments to mathematically prove that the VU pipeline strictly complies with the RISC-V Vector (V) Extension specification. Simulation Partnership: Collaborate closely with VU simulation engineers to define a razor-sharp boundary between simulation and formal verification, ensuring maximum bug-hunting efficiency and zero coverage gaps. Embedded Mentorship & Best Practices (10%) Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns. SVA Propagation: Review and refine SystemVerilog Assertions (SVA) written by design and simulation peers, establishing best practices for block-level assertions within the VU team. Education: B.S./M.S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution; or a Ph.D. with a research focus on formal methods or computer arithmetic. Experience: 5+ years of production-grade hardware verification experience (or Ph.D. + 1–3 years) with a strong, proven track record of applying formal verification to CPU, GPU, or DSP execution pipelines. Collaboration Style: A self-driven engineer who enjoys deep mathematical puzzles, collaborates seamlessly within a localized block-level team, and can translate complex proof counter-examples into actionable bugs for designers. Datapath Validation Focus: Strong specialization in arithmetic formal verification, algebraic rewriting, and word-level modeling. Familiarity with control-path formal techniques (liveness, safety properties) is highly welcome. Vector Microarchitecture: Good working knowledge of high-width execution pipelines, vector execution units, or floating-point/integer arithmetic hardware. Experience with Out-of-Order execution mechanics is a plus. Formal Tools: Proficient command of commercial EDA formal tools (e.g., Cadence JasperGold/DPV, Synopsys VC Formal, Siemens OneSpin) and their specialized mathematical/datapath apps. Languages: Native fluency in SystemVerilog and SystemVerilog Assertions (SVA). Scripting proficiency (Python, Tcl, or Bash) for testbench automation. Nice to Have RISC-V Core Verification. RISC-V Ecosystem: Familiarity with the RISC-V Architecture, specifically the Vector (V) and Floating-Point (F/D) extension ecosystems. Emulation platforms (Veloce, ZeBu). Core/Bus interface protocols (e.g., AXI/CHI).

Location: Barcelona, Spain; Bordeaux, France; Grenoble, France; Lille, France; Lyon, France; Montpellier, France; Nantes, France; Paris, France; Toulouse, France; Bolzano, Italy; Rome, Italy; Aachen, Germany; Augsburg, Germany; Bad Homburg, Germany; Baden-Baden, Germany; Bergisch Gladbach, Germany; Berlin, Germany; Darmstadt, Germany; Bramsche, Germany; Bielefeld, Germany; Bernau, Germany; Chemnitz, Germany; Dresden, Germany; Dusseldorf, Germany; Düsseldorf, Germany; Geoergsmarienhütte, Germany; Freiburg, Germany; Frankfurt, Germany; Essen, Germany; Atlanta, United States; Austin, United States; Boca Raton, United States; Boston, United States; Chicago, United States; Columbus, United States; Dallas, United States; Detroit, United States; Florida City, United States; Houston, United States; Los Angeles, United States; Kirkland, United States; Kansas City, United States; Indianapolis, United States; Miami, United States; Milwaukee, United States; Minneapolis–Saint Paul, United States; New York, United States; Newark, United States; Redmond, United States; Sacramento, United States; San Francisco, United States; San Jose, United States; Seattle, United States; St. Louis, United States; Richmond, United States; Vacaville, United States; Tampa, United States; Fatorda, India; Hyderabad, India; Bangalore, India; Mumbai, India; Pondicherry, India; Ahmedabad, India; Delhi, India; Batumi, Georgia; Tbilisi, Georgia; Antalya, Türkiye; Porto, Portugal; Lisbon, Portugal; Buenos Aires, Argentina Workplace: remote At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a IP Verification Engineer to join one of our clients ' teams. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you. Responsibilities: Develop a verification plan based on the specification. Build verification infrastructure for the block. Develop tests, stimulus, and checkers based on the test plan. Achieve 100% regression and functional coverage. University degree in Electrical Engineering or a related field. 5+ years of experience in UVM-based verification of complex IPs. Proficiency in developing verification environments from scratch. Knowledge of AXI protocols. Nice to have prior experience in verification of multicore designs.