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Location: Petten, Netherlands; Pondicherry, India; Aachen, Germany; Abidjan, Côte d'Ivoire; Abu Dhabi, United Arab Emirates; Ahmedabad, India; Alexandria, Egypt; Algiers, Algeria; Alkmaar, Netherlands; Almaty, Kazakhstan; Amersfoort, Netherlands; Amsterdam, Netherlands; Antalya, Türkiye; Astana, Kazakhstan; Athens, Greece; Augsburg, Germany; Aya Napa, Cyprus; Bad Homburg, Germany; Baden-Baden, Germany; Baku, Azerbaijan; Bangkok, Thailand; Barcelona, Spain; Batumi, Georgia; Belgrade, Serbia; Bergisch Gladbach, Germany; Berlin, Germany; Bernau, Germany; Bielefeld, Germany; Birmingham, United Kingdom; Bishkek, Kyrgyzstan; Boca Raton, United States; Bolzano, Italy; Bordeaux, France; Boston, United States; Bramsche, Germany; Bratislava, Slovakia; Bromolla, Sweden; Brussels, Belgium; Bryanston, South Africa; Bucharest, Romania; Bucuresti, Romania; Budapest, Hungary; Buenos Aires, Argentina; Cairo, Egypt; Cape Town, South Africa; Cebu City, Philippines; Chemnitz, Germany; Chicago, United States; Santiago, Chile; Beijing, China; Chișinău, Moldova, Republic of; Bogota, Colombia; Colombo, Sri Lanka; Columbus, United States; Copenhagen, Denmark; Costa Rica; Havana, Cuba; Dakar, Senegal; Dallas, United States; Dammam, Saudi Arabia; Darmstadt, Germany; Davao City, Philippines; Delhi, India; Detroit, United States; Mirpur, Bangladesh; Djibouti; Dnipro, Ukraine; Douala, Cameroon; Dresden, Germany; Dubai, United Arab Emirates; Dublin, Ireland; Dusseldorf, Germany; Düsseldorf, Germany; Guayaquil, Ecuador; Emmen, Switzerland; London, United Kingdom; Erevan, Armenia; Essen, Germany; Fatorda, India; Helsinki, Finland; Florida City, United States; Frankfurt, Germany; Freiburg, Germany; Gatineau, Canada; Geoergsmarienhütte, Germany; Görlizt, Germany; Göttingen, Germany; Greifswald, Germany; Grenoble, France; Guadalajara, Mexico; Guatemala; Gżira, Malta; Halle, Germany; Hamburg, Germany; Hannover, Germany; Heinsberg, Germany Workplace: remote At TechBiz Global , we are providing recruitment service to our TOP clients from our portfolio. We are currently looking for a DFT & Post-Silicon Validation to join one of our clients' team Are you passionate about Design for Testability (DFT) for complex SoCs and SoC chiplets in package? We need you! As a Senior DFT and Post-Silicon Lead, you will own the DFT implementation process, ensuring seamless integration with test and post-silicon validation teams. You will work with cutting-edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production. Key Responsibilities Leadership & Team Management Lead and mentor the DFT and Post-Silicon engineering teams to drive innovation and efficiency. Provide technical direction, ensuring alignment with organizational goals. Foster a culture of continuous improvement and collaboration. DFT Strategy & Execution Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability. Ensure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces. Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield. Test Development & Implementation Develop and implement test plans and test strategies at silicon, package, and system levels. Define and develop automated test solutions for production and characterization. Ensure test coverage for all product development stages, from pre-silicon to mass production. Guarantee high yield on the final solution while considering chiplet complexities. Cross-Functional Collaboration Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability. Collaborate with product management to ensure alignment with customer requirements and timelines. Process Improvement & Innovation Continuously explore and implement new DFT methodologies and manufacturing processes. Lead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production. Reporting Structure Reports to: Physical Implementation Team Manager Receives reports from: DFT and Post-Silicon team members Bachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field. Proven experience with multiple tape-outs of high-performance SoCs or SiPs for mass production. Strong background in post-silicon test optimization and yield analysis. Experience in defining and implementing test strategies for high-volume production. Proficiency in RTL and testbench development using SystemVerilog and Verilog. Strong scripting skills (Shell, Tcl, Python3). Hands-on experience with Tessent and SSN methods integrated with leading EDA design flows for advanced technology nodes is a plus.

Location: Israel; United Kingdom; France; Germany; Netherlands; Mexico About us At SPD Technology, we bring together a team of like-minded people who are driven by the desire to bring value through their work, united in their commitment to high performance and delivering custom, cutting-edge tech solutions that drive clients' growth. We empower our people with a culture of excellence, and enable them with the opportunity to uphold their accountability to contribute on each level. We value humanity and collaboration, encourage professional and personal growth, and foster a supportive and flexible work environment where everyone's contribution is welcomed. We are looking for a Signal Integrity/Power Integrity Engineer to join us as part of our team. About the role As a Signal Integrity/Power Integrity Engineer you will work to shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology that powers the most demanding AI/ML applications. You will be part of a team developing custom silicon solutions, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You will lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production, while collaborating within a cross-functional team of Chip Design, IP, System Design, software, and vendors. As a qualified expert You will Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) leveraging advanced 2.5D/3D packaging technologies. Partner early in product definition to influence chip floorplanning, power distribution networks (PDN/power trees), netlists, and routability tradeoffs. Evaluate high-speed interface IPs and develop next-generation memory interfaces across IO PHY, SI/PI, and physical design boundaries. Drive post-silicon validation and qualification for NPI, balancing SI/PI performance and DFM constraints to achieve final package design closure. Partner closely with silicon, system, and external vendor teams while developing simulation methodologies to boost modeling accuracy and efficiency. We're looking for you if you have Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in SI/PI design for chip/package or system PCB. Experience in industry SIPI modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.). Experience with lab bring-up, test environments, and characterization for high-speed memory and SerDes. Experience with partnering across chip architecture, physical design, static timing analysis (STA), package, and validation teams. Experience in Python, MATLAB, or C++ to establish automated flows and data processing tools. Bonus points Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Deep knowledge of SI/PI analysis for high-speed interconnects (HBMx, D2D/chiplets, PCIe, SerDes) and timing budget methodologies. Direct experience with silicon interposers, silicon bridges, and 3D die stacking architectures. What's in it for You Reveal great tech solutions Join the team of experts who create custom, cutting-edge tech solutions for world-renowned businesses, fueling clients growth. Unleash your potential, tackle new challenges, and be part of a team that values your skills and contributions. Focus on long-term impact and building tailored, long-lasting partnerships with our clients. Experience an agile and flexible working environment Work fully remote around the globe, or in a hybrid work model from our office hubs which are equipped with everything needed for comfortable work. Enjoy a flexible working schedule and create work and rest balance for yourself. Empower yourself with a stable workload and a stable income, focusing on lasting cooperation and high-performance culture. Embrace the opportunity for personal and professional growth Take advantage of performance review and career path. Elevate your skills with mentorship program, personal development plan, and individual learnings through the corporate library, public speaking support, and more. Feel cared about Be among like-minded people and feel supported with collaboration, open communication and mutual respect. Join company-wide tech and cultural events, and contribute to meaningful CSR initiatives that resonate with your values. Interview steps Interview with Recruiter Manager Interview Client Interview

Location: Palo Alto, United States 📍 Location: Palo Alto, CA 📄 Employment Type: Contract 🏢 Work Arrangement: On-site 🚀 Start Date: TBD 💰 Compensation: TBD — based on skills and experience Important Screening Requirements 5+ years of experience in post-silicon characterization, high-speed I/O (HSIO) validation, or memory electrical validation. Hands-on experience characterizing high-speed SerDes PHYs , particularly PCIe. Experience measuring eye diagrams, jitter, bit error rate (BER), and S-parameters . Proficiency with high-speed oscilloscopes, bit error rate testers (BERT), and VNA/TDR equipment. Ability to read and interpret schematics and PCB layouts. Experience debugging electrical issues directly at the probe point. Python scripting experience for laboratory test automation. Background in semiconductor, silicon, or systems companies, including SoC, GPU, networking, storage, or automotive compute. Must be willing to work on-site in Palo Alto, CA . About the Role We are seeking a hands-on PCIe Characterization Engineer to perform post-silicon electrical characterization and validation of high-speed SerDes physical-layer interfaces in a laboratory environment. The role focuses on conducting high-speed electrical measurements, analyzing signal integrity, and validating silicon performance. You will independently operate laboratory equipment, troubleshoot signal-level issues, interpret hardware schematics and PCB layouts, and automate characterization workflows using Python. The successful candidate will have direct experience with high-speed interface characterization and the practical skills needed to investigate electrical performance issues at the measurement and probe points. What We’re Looking For We’re looking for an experienced post-silicon characterization or HSIO validation engineer with strong hands-on laboratory skills and practical knowledge of high-speed electrical measurements. The ideal candidate can independently perform eye, jitter, BER, and S-parameter measurements; operate high-speed test equipment; interpret schematics and layouts; and troubleshoot signal integrity issues directly in the lab. Strong candidates will combine experience with PCIe and SerDes interfaces, high-speed measurement instrumentation, electrical debugging, and Python-based lab automation . Key Responsibilities Post-Silicon Characterization & Validation Perform post-silicon electrical characterization of high-speed SerDes PHYs, including: PCIe Ethernet UFS LPDDR5 Support high-speed interface validation and investigate electrical performance issues. Analyze characterization results to assess high-speed interface performance. Identify and troubleshoot signal-level issues during testing. High-Speed Electrical Measurements Conduct eye diagram, jitter, bit error rate (BER), and S-parameter measurements . Independently operate laboratory measurement equipment, including: High-speed oscilloscopes Bit error rate testers (BERT) Vector network analyzers (VNA) Time-domain reflectometry (TDR) equipment Analyze measurement data to evaluate electrical performance and signal integrity. Document test configurations, measurement results, and characterization findings. Schematic Analysis & Electrical Debugging Read and interpret electrical schematics and PCB layouts to support characterization activities. Troubleshoot signal integrity and electrical issues directly at probe points. Investigate measurement anomalies and high-speed interface performance problems. Apply practical electrical measurement and debugging techniques to identify potential issues. Python Lab Automation Develop and maintain Python scripts to automate laboratory measurements and characterization workflows. Support repeatable and efficient execution of electrical tests. Improve laboratory testing efficiency through reusable automation scripts. Assist with measurement data collection, analysis, and documentation. Cross-Functional Validation Support Support high-speed interface validation activities across relevant silicon and systems platforms. Collaborate with engineering teams to investigate electrical performance issues. Communicate measurement findings, debugging results, and characterization progress. Maintain clear technical documentation of test procedures, configurations, and results. Required Qualifications 5+ years of experience in post-silicon characterization, HSIO validation, or memory electrical validation. Experience working at a semiconductor, silicon, or systems company in areas such as SoC, GPU, networking, storage, or automotive compute. Hands-on experience with high-speed SerDes PHY characterization. Practical experience measuring eye diagrams, jitter, BER, and S-parameters. Proficiency using high-speed oscilloscopes, BERT, and VNA/TDR equipment. Experience reading and interpreting schematics and PCB layouts. Strong laboratory debugging and electrical measurement skills. Python scripting experience for test and measurement automation. Strong analytical, troubleshooting, and problem-solving abilities. Willingness to work on-site in Palo Alto, CA. Preferred Qualifications Experience with PCIe electrical characterization and validation . Exposure to Ethernet, UFS, or LPDDR5 interfaces. Experience with high-speed signal integrity measurements and analysis. Background in silicon validation for SoC, GPU, networking, storage, or automotive-compute products. Experience developing reusable automation scripts and improving laboratory test efficiency.

Location: United States Location: Palo Alto, CA (On-site) Job Type: Contract Job Overview We are seeking an experienced PCIe Characterization Engineer to perform post-silicon electrical characterization and validation of high-speed SerDes PHYs. This role involves hands-on laboratory testing, electrical measurement, signal integrity analysis, and debugging of high-speed interfaces across PCIe, Ethernet, UFS, and LPDDR5 technologies. The ideal candidate has a strong background in post-silicon characterization or high-speed I/O (HSIO) validation, with practical experience using advanced lab equipment and developing Python scripts for test automation. Key Responsibilities Perform post-silicon electrical characterization of high-speed SerDes PHYs and memory interfaces. Conduct eye diagram, jitter, bit error rate (BER), and S-parameter measurements. Operate high-speed oscilloscopes, bit error rate testers (BERT), vector network analyzers (VNA), and TDR equipment. Analyze schematics and PCB layouts to identify signal integrity issues and support electrical debugging. Perform hands-on troubleshooting and debug at the probe point to isolate and resolve hardware-level issues. Develop and maintain Python scripts for laboratory test automation, data collection, and analysis. Analyze characterization results, document findings, and collaborate with cross-functional engineering teams to improve interface performance. Support validation activities for high-speed interfaces, including PCIe, Ethernet, UFS, and LPDDR5. Required Qualifications 5+ years of experience in post-silicon characterization, HSIO validation, SerDes validation, or memory electrical validation. Hands-on experience characterizing high-speed electrical interfaces in a semiconductor or systems engineering environment. Proficiency with high-speed oscilloscopes, BERT, VNA, and/or TDR measurement equipment. Practical experience measuring and analyzing eye diagrams, jitter, BER, and S-parameters. Ability to read and interpret schematics and PCB layouts for hardware-level debugging. Experience with Python scripting for laboratory automation and test data analysis. Strong troubleshooting, analytical, and problem-solving skills. Ability to work on-site in Palo Alto, California. Preferred Qualifications Experience with PCIe, Ethernet, UFS, LPDDR5, or other high-speed SerDes and memory interfaces. Background working with SoCs, GPUs, networking hardware, storage systems, or automotive computing platforms. Experience with signal integrity analysis and post-silicon hardware validation. Previous experience in semiconductor, silicon design, or systems companies. Ideal Candidate Profile Candidates with titles such as PCIe Characterization Engineer, Signal Integrity Engineer, HSIO Validation Engineer, Post-Silicon Validation Engineer, or SerDes Validation Engineer are encouraged to apply. Candidates currently based in the San Francisco Bay Area are strongly preferred due to the on-site nature of the position.

Location: San Francisco, CA | New York City, NY About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role Anthropic is building custom silicon for Claude. The hardware our models run on is one of the most direct levers we have on capability, cost, and reliability — and we've decided to take design authority over it ourselves. We're looking for a Technical Program Manager to own end-to-end execution of our silicon, from architecture definition through tapeout, first-silicon bring-up, and production ramp. You'll be working alongside a small group of domain experts across front-end design, verification, physical design, DFT, analog/mixed-signal, foundry, and packaging. There is no process to inherit — you'll build the execution machinery this program runs on. This is a partner-heavy program by design. You'll drive a portfolio of external engagements — ASIC design services, IP vendors, foundry, and OSAT. You should have shipped chips before, know what a realistic silicon schedule looks like and its failure modes, and be comfortable making consequential program calls without a large organization behind you. And because this is Anthropic, you'll have Claude as a collaborator — we expect the TPMs on this team to push hard on what AI-assisted program management can look like. Key responsibilities Own the integrated silicon program plan — architecture closure, RTL freeze, DV milestones, IP delivery, PD closure, DFT, tapeout, and post-silicon bring-up. Drive external partner execution across ASIC design partners, IP vendors, foundry, and packaging/test. Run technology and IP selection as a program: track candidate vendors and options, drive evaluations to a decision, and land the build / buy / license calls with engineering leadership. Build the execution mechanisms a silicon team needs — milestone definitions, risk and dependency tracking, design reviews, release management, exec reporting — and keep them lightweight enough that engineers actually use them. Manage the interface between silicon and its consumers: hardware systems for package/board/bring-up, and inference/kernels/compiler teams for hardware-software co-design, so trade-offs land as coordinated decisions rather than late surprises. Own the post-silicon program — bring-up planning, ATE/test handoff, sample distribution, validation, and the path to production readiness. Develop and share AI-assisted approaches to program management — schedule and dependency modeling, spec and milestone consistency checking, partner-deliverable tracking, status synthesis. Minimum qualifications 8+ years in silicon/SoC program management, chip lead, or an equivalent role that owned a chip schedule end to end. Direct ownership of at least one program that taped out and reached production, with milestones you can speak to in detail — including where it slipped and what you did about it. Working technical fluency across the silicon lifecycle — front-end, DV, PD, DFT, foundry, packaging. Experience running external silicon partners — ASIC houses, IP vendors, foundry, or OSAT — including SOW scoping, delivery tracking, and escalation. Track record of building program mechanisms from scratch on an ambiguous, fast-moving effort. Strong written communication — plans, reviews, and exec updates that many teams depend on. Comfort operating with high autonomy and limited process on a highly dynamic program. Preferred qualifications Experience on ML accelerators, high-performance compute, networking, or other large, high-bandwidth SoCs at advanced process nodes. Experience on a first-generation or early silicon program, including standing up flows, methodology, or vendor relationships from nothing. Experience with both partner-executed and fully in-house programs, and a view on the trade-offs between them. Prior hands-on engineering background in one or more silicon domains (design, DV, PD, DFT, or SI/PI). Familiarity with the chip-package-system interface and co-design with a hardware systems team. Experience with hardware-software co-design programs — working directly with compiler, kernel, or runtime teams. Practical experience using AI tools in your own workflow, and clear ideas about where they help and where they don't. BS/MS in EE, CE, CS, or a related field, or equivalent experience. The annual compensation range for this role is listed below. For sales roles, the range provided is the role’s On Target Earnings ("OTE") range, meaning that the range includes both the sales commissions/sales bonuses target and annual base salary for the role. Annual Salary: $365,000 — $435,000 USD Logistics Minimum education: Bachelor’s degree or an equivalent combination of education, training, and/or experience Required field of study: A field relevant to the role as demonstrated through coursework, training, or professional experience Minimum years of experience: Years of experience required will correlate with the internal job level requirements for the position Location-based hybrid policy: Currently, we expect all staff to be in one of our offices at least 25% of the time. However, some roles may require more time in our offices. Visa sponsorship: We do sponsor visas! However, we aren't able to successfully sponsor visas for every role and every candidate. But if we make you an offer, we will make every reasonable effort to get you a visa, and we retain an immigration lawyer to help with this. We encourage you to apply even if you do not believe you meet every single qualification. Not all strong candidates will meet every single qualification as listed.  Research shows that people who identify as being from underrepresented groups are more prone to experiencing imposter syndrome and doubting the strength of their candidacy, so we urge you not to exclude yourself prematurely and to submit an application if you're interested in this work. We think AI systems like the ones we're building have enormous social and ethical implications. We think this makes representation even more important, and we strive to include a range of diverse perspectives on our team. Your safety matters to us. To protect yourself from potential scams, remember that Anthropic recruiters only contact you from @anthropic.com email addresses. In some cases, we may partner with vetted recruiting agencies who will identify themselves as working on behalf of Anthropic. Be cautious of emails from other domains. Legitimate Anthropic recruiters will never ask for money, fees, or banking information before your first day. If you're ever unsure about a communication, don't click any links—visit anthropic.com/careers directly for confirmed position openings. How we're different We believe that the highest-impact AI research will be big science. At Anthropic we work as a single cohesive team on just a few large-scale research efforts. And we value impact — advancing our long-term goals of steerable, trustworthy AI — rather than work on smaller and more specific puzzles. We view AI research as an empirical science, which has as much in common with physics and biology as with traditional efforts in computer science. We're an extremely collaborative group, and we host frequent research discussions to ensure that we are pursuing the highest-impact work at any given time. As such, we greatly value communication skills. The easiest way to understand our research directions is to read our recent research. This research continues many of the directions our team worked on prior to Anthropic, including: GPT-3, Circuit-Based Interpretability, Multimodal Neurons, Scaling Laws, AI & Compute, Concrete Problems in AI Safety, and Learning from Human Preferences. Come work with us! Anthropic is a public benefit corporation headquartered in San Francisco. We offer competitive compensation and benefits, optional equity donation matching, generous vacation and parental leave, flexible working hours, and a lovely office space in which to collaborate with colleagues. Guidance on Candidates' AI Usage: Learn about our policy for using AI in our application process.