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Задачи: — Разработка ПО для вычислительных модулей с архитектурой x86, ARM, MIPS для различных дистрибутивов Linux. — Разработка тестового ПО для работы в ОС Linux. — Взаимодействие с hardware инженерами при отладке новых изделий. — Функциональное тестирование и отладка разработанного программного обеспечения. — Техническая поддержка подразделения сервисного обслуживания. Требования: — Высшее образование (информатика и вычислительная техника, ЭВМ, прикладная математика, АСУ, РЭА и т.п.). — Знание Python, C/С++, cmake. — Умение работать в CLI, знание базовых утилит, опыт написания shell-скриптов. — Опыт программирования в среде Linux. — Умение работать с системой контроля версий git. — Опыт эксплуатации систем виртуализации, контейнеризации. — Опыт работы c CI/CD. Приветствуется: — Опыт разработки под ОС Эльбрус, Baikal. — Опыт применения инструментов совместной разработки (GitLab, Jira, Confluence и т.п). — Опыт написания модулей ядра/драйверов Linux. — Понимание работы шин UART, I2C, SPI, USB, PCIe. — Глубокое знание сетевых технологий. — Знакомство с внутренним устройством сетевых коммутаторов (протоколы, встраиваемое ПО и т.д.). Условия: — Работа в успешной компании в команде интересных, увлеченных своим делом людей. — Трудоустройство по ТК РФ и достойную заработную плату – размер обсуждается на собеседовании в зависимости от квалификации кандидата. — Обед на оборудованной кухне или в столовой (демократичные цены). — ДМС после завершения испытательного срока. — Работа в офисе в шаговой доступности от метро Беляево (3 мин пешком).

Задачи: • Разработка и отладка RTL на Verilog • Разработка управляющего ПО на C (Microblaze, Vitis) • Интеграция P4-логики • Интеграция и настройка IP-ядер в Vivado • Реализация протоколов: 10G Ethernet, UDP, IPv4/IPv6, PTP (IEEE 1588), SyncE • Работа с интерфейсами: AXI4-MM / Stream / Lite • Интеграция 10G, DDR4, PCIe (XDMA), SPI, I2C • Оптимизация высокоскоростных трактов Требования: • Уверенный Verilog • Опыт разработки на C • Понимание архитектуры FPGA (Xilinx) • Опыт работы с Vivado / Vitis • Понимание Ethernet и UDP/IP • Опыт работы с AXI • Опыт интеграции 10G и PCIe Плюсом будет: • Опыт реализации PTP Transparent Clock (P2P / E2E) • Опыт работы с SyncE • Реализация WRED или других congestion control алгоритмов • Оптимизация high-speed datapath • Аппаратная обработка сетевого трафика Условия: • Официальное трудоустройство

Задачи: — Проведение функционального, интеграционного, регрессионного и нагрузочного тестирования — Разработка и оптимизация тестовой модели — Анализ дефектов, взаимодействие с отделом разработки для их устранения — Подготовка технической документации (тест-планы, отчеты, ПМИ/ПСИ) — Участие в отладке BIOS/UEFI/BMC, взаимодействие с аппаратными компонентами — Техническая поддержка заказчиков и производственных линий Требования: — Опыт работы от 5 лет в тестировании сложных аппаратно-программных систем, из них не менее двух лет в тестировании серверных платформ, желательно на платформе Intel gen4/5 — Опыт написания и актуализации тестовых моделей с использованием техник тест-дизайна — Опыт работы в команде разработки Hardware + Software — Опыт тестирования высокоскоростных интерфейсов: PCIe, USB 3.0/4.0, Ethernet 1G/10G/25G/100G, DDR4/DDR5 ECC, SATA/SAS/NVMe, U2, LVDS, MCIO, OCP — Участие в ОКР: разработка ТЗ, подготовка документации, проведение испытаний, анализ результатов — Глубокое знание состава и принципов работы аппаратных компонентов оборудования (персональных компьютеров, серверов, СХД) — Знание HBA/RAID контроллеров, различных сетевых карт, практические навыки тестирования совместимости компонентов — Умение работать с dbus, IPMI, Redfish — Работа с протоколами: I2C, SMBus, UART, SPI, JTAG — Отладка на стендах, поддержка производства Условия: — Работа в крупном инвестиционно-промышленном холдинге, участие в уникальных проектах — Оформление по ТК РФ с первого рабочего дня, социальные гарантии — ДМС после прохождения испытательного срока — Стабильная заработная плата: оклад + премии — Гибкое начало и окончание рабочего дня — Расположение офиса в 6 минутах от м. ВДНХ — Работа в молодом, энергичном и творческом коллективе

Location: Remote - London MinIO is the data and memory foundation for enterprise AI. Built for the speed, scale, and economics that AI and analytics demand, AIStor and MemKV unify every layer of the data stack, from agentic and inference context memory to tables and objects across core, edge, and cloud. Trusted by 77% of the Fortune 100, MinIO is redefining how AI factories, intelligent applications, and autonomous agents secure, persist, and unlock the full value of their data. The European cloud landscape is undergoing a massive structural shift. Specialized GPU cloud providers, alternative infrastructure platforms, and sovereign cloud consortiums—collectively known as NeoClouds —are scaling exponentially to fuel the generational demand for enterprise AI/ML training and inference. As an Account Executive for the NeoCloud market in Europe, you will own MinIO’s commercial footprint across this hyper-growth sector. This role is open as a remote role in any Major European AI Hub for a qualified candidate. You will be selling a revolutionary AI data infrastructure portfolio, headlined by: MinIO AIStor: Our exascale AI data store purpose-built for massive concurrency, sub-10ms latency, and high-throughput training pipelines. MinIO MemKV: Our purpose-built context memory store that eliminates the inference "recompute tax" by turning NVMe flash into a shared memory tier that GPU pods access at microsecond speeds over RDMA. Why this role matters: AI infrastructure cannot achieve true efficiency using legacy storage frameworks. By positioning MinIO at the foundation of European NeoClouds, you will directly enable cloud providers to maximize GPU utilization (95%+), collapse time-to-first-token latencies from seconds to milliseconds, and drastically lower operational costs for their enterprise tenants. What You Will Do Drive Revenue & Market Share: Execute a strategic enterprise sales motion to identify, sign, and expand high-value commercial partnerships with European NeoClouds, specialized AI hosters, and sovereign cloud providers. Value-Based Portfolio Positioning: Lead complex technical and business conversations illustrating how MinIO products meet current and future requirements. Full Sales Lifecycle Management: Actively manage the end-to-end sales pipeline, from prospecting and initial technical qualification to executive alignment, pilot orchestration, pricing architecture, and contract closure. Cross-Functional Alignment: Collaborate closely with MinIO Solution Architects, Product Engineering, and corporate leadership to handle demanding infrastructure environments involving S3 over RDMA, PCIe Gen6, and NVIDIA reference architectures (e.g., Spectrum-X Ethernet, BlueField-4 STX). Ecosystem Amplification: Leverage alliances with key physical hardware and networking providers (e.g., NVIDIA, regional data center developers) to position MinIO as the foundational storage choice for modern AI deployment blueprints. Your Skills and Experience Proven Infrastructure Sales Record: 10+ years of quota-carrying enterprise software sales experience, with a documented history of successfully selling to cloud service providers (CSPs), telcos, managed services providers (MSPs), or high-performance computing (HPC) hubs. Familiarity with NVIDIA ecosystem:  AI Factory architecture and experience selling with NVIDIA field teams is a huge plus. Deep AI/ML Infrastructure Literacy: Fluency in the mechanics of modern AI infrastructure stacks. You can confidently discuss GPUs, Kubernetes operators, high-speed networking fabrics (RDMA/InfiniBand), KV Cache eviction challenges in LLMs, and modern data platforms like Apache Iceberg. Strategic Deal Architect: Proven ability to navigate complex, multi-layered corporate accounts, building deep trust with everyone from infrastructure engineers to executive decision-makers (CTOs, CEOs, Heads of AI Infrastructure). European Landscape Expertise: Strong understanding of regional dynamics within European tech markets (UK, DACH, France, Benelux, Nordics) and the data sovereignty requirements reshaping the continent's infrastructure policies. Entrepreneurial Engine: A proactive, self-motivated operator who thrives in high-velocity, high-innovation spaces and enjoys building a market segment from the ground up. Equal Opportunity Policy (EEO) MinIO is proud to be an equal opportunity workplace and an affirmative action employer. We review applications for employment without regard to their race, color, religion, sex, sexual orientation, gender identity, national origin, ancestry, citizenship, age, veteran status, genetic information, physical or mental disability, medical condition, marital status, or any other basis prohibited by law.

Location: Costa Mesa, United States ABOUT THE ROLE We are seeking an experienced Senior E MI/EMC Engineer to join our Air Dominance & Strike Electrical Engineering team. The ideal candidate will be responsible for designing, testing, and validating electromagnetic compatibility (EMC) and electromagnetic interference (EMI) solutions for electronic products. This role involves collaborating with cross-functional teams to ensure compliance with industry standards and regulatory requirements. WHAT YOU'LL DO Conduct EMI/EMC testing and analysis on electronic systems and components. Drive product maturity through rapid prototyping, design verification, and qualification activities. Develop and implement design strategies to mitigate EMI/EMC issues. Prepare test plans, reports, and documentation for compliance verification. Collaborate with product design teams to ensure EMC requirements are integrated during the design phase. Identify program EMI/EMC risks and define strategies for reducing risk through the definition of modeling, simulation, or experimental activities. Stay updated on relevant standards (e.g., MIL-STD-461G, MIL-STD-464D, DOD-160, FCC, CISPR, IEC) and regulatory requirements. Conduct field tests and assessments to evaluate product performance in real-world environments. Work in a fast-paced environment, having to juggle multiple concurrent projects and customers. REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Electronics, or a related field. 7+ years of experience in EMI/EMC design and testing. Familiarity with EMC/EMI standards and regulations (e.g., MIL-STD-461G, MIL-STD-464D, RTCA DOD-160, FCC, IEC, CISPR, SAE). Proven expertise in E3 design, analysis, testing and mitigation strategies. Specialized in HERO, HEMP, Lightning Protection, ESD, RF exposure limits and operational electromagnetic compatibility. Proficiency in using EMI/EMC testing equipment (e.g., spectrum analyzers, oscilloscopes, antennas, LISN etc.) Experience with simulation tools (e.g., ANSYS, CST Microwave Studio) for EMI analysis. Strong analytical and troubleshooting skills for identifying and resolving EMI/EMC issues. Excellent verbal and written communication skills for reporting findings and collaborating with teams. Ability to manage multiple projects and meet deadlines in a fast-paced environment. Full understanding of PCB Layout techniques to meet mechanical, electrical, EMI/EMC, and manufacturing requirements. Ability to read and interpret schematics and apply best practices appropriate for each design. Familiarity with standard interfaces such as MIPI, DP, I2C, SPI, PCIe, USB, etc. Must be able to obtain and maintain a DoD Secret Clearance

Location: Costa Mesa, United States ABOUT THE JOB We are looking for a FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA . You will own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, with a focus on UVM-based methodology and coverage-driven verification. This will require expertise in SystemVerilog, object-oriented programming, and UVM. If you are someone who has supported rapid avionics development, then this role is for you. WHAT YOU’LL DO Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs Develop verification plans with traceability to system and hardware requirements Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks Build functional coverage models and drive code coverage analysis to closure Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs Establish and maintain regression suites, tracking coverage metrics and verification progress Debug failures using waveform tools and simulation logs at the HDL and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement Support hardware validation and board bring-up on target platforms Ensure verification meets DO-254 and relevant safety standards Author verification closure reports and coverage analysis summaries REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 2+ years of experience in FPGA/ASIC verification Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches Object-oriented programming principles Industry simulators (Questa, VCS, Xcelium, or Vivado) Git-based collaborative workflows including code review Linux development environments Strong communication and teamwork skills Eligible to obtain and hold a U.S. Secret security clearance PREFERRED QUALIFICATIONS 5+ years of experience in FPGA/ASIC verification Master’s degree in Electrical Engineering, Computer Engineering, or related field DO-254, avionics verification standards for UAS, and safety-critical verification processes SVUnit or equivalent unit-testing frameworks Formal verification or CDC verification tools Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI Verification automation scripting (Python, Tcl, Makefile) SoC and ARM-based embedded platforms Verification automation, CI/CD integration, and Nix-based build environments

Location: Costa Mesa, United States WHAT YOU’LL DO Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs Develop verification plans with traceability to system and hardware requirements Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks Build functional coverage models and drive code coverage analysis to closure Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs Establish and maintain regression suites, tracking coverage metrics and verification progress Debug failures using waveform tools and simulation logs at the HDL and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement Support hardware validation and board bring-up on target platforms Ensure verification meets DO-254 and relevant safety standards Author verification closure reports and coverage analysis summaries REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 2+ years of experience in FPGA/ASIC verification Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches Object-oriented programming principles Industry simulators (Questa, VCS, Xcelium, or Vivado) Git-based collaborative workflows including code review Linux development environments Strong communication and teamwork skills Eligible to obtain and hold a U.S. Secret security clearance PREFERRED QUALIFICATIONS 5+ years of experience in FPGA/ASIC verification Master’s degree in Electrical Engineering, Computer Engineering, or related field DO-254, avionics verification standards for UAS, and safety-critical verification processes SVUnit or equivalent unit-testing frameworks Formal verification or CDC verification tools Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI Verification automation scripting (Python, Tcl, Makefile) SoC and ARM-based embedded platforms Verification automation, CI/CD integration, and Nix-based build environments

Location: Barcelona, Spain; Petten, Netherlands; Pondicherry, India; Aachen, Germany; Abidjan, Côte d'Ivoire; Abu Dhabi, United Arab Emirates; Ahmedabad, India; Berat, Albania; Alexandria, Egypt; Algiers, Algeria; Alkmaar, Netherlands; Almaty, Kazakhstan; Amersfoort, Netherlands; Amman, Jordan; Amsterdam, Netherlands; Antalya, Türkiye; Astana, Kazakhstan; Asunción, Paraguay; Athens, Greece; Augsburg, Germany; Aya Napa, Cyprus; Bad Homburg, Germany; Baden-Baden, Germany; Baku, Azerbaijan; Bangkok, Thailand; Batumi, Georgia; Belgrade, Serbia; Bergisch Gladbach, Germany; Berlin, Germany; Bernau, Germany; Bielefeld, Germany; Birmingham, United Kingdom; Bishkek, Kyrgyzstan; Bolzano, Italy; Bordeaux, France; Bramsche, Germany; Bratislava, Slovakia; Bromolla, Sweden; Brussels, Belgium; Bryanston, South Africa; Bucharest, Romania; Bucuresti, Romania; Budapest, Hungary; Cairo, Egypt; Cebu City, Philippines; Chemnitz, Germany; Santiago, Chile; Beijing, China; Chișinău, Moldova, Republic of; Bogota, Colombia; Colombo, Sri Lanka; Copenhagen, Denmark; Costa Rica; Havana, Cuba; Darmstadt, Germany; Davao City, Philippines; Delhi, India; Mirpur, Bangladesh; Djibouti; Dnipro, Ukraine; Dresden, Germany; Dublin, Ireland; Dusseldorf, Germany; Düsseldorf, Germany; Emmen, Switzerland; London, United Kingdom; Erevan, Armenia; Essen, Germany; Fatorda, India; Helsinki, Finland; Frankfurt, Germany; Freiburg, Germany; Geoergsmarienhütte, Germany; Görlizt, Germany; Göttingen, Germany; Greifswald, Germany; Grenoble, France; Gżira, Malta; Halle, Germany; Hamburg, Germany; Hannover, Germany; Heinsberg, Germany; Crete, Greece; Ho Chi Minh, Vietnam; Hyderabad, India; istanbul, Türkiye; Istambul, Türkiye; Istanbul, Türkiye; Ankara, Türkiye; Mumbai, India; Karlsruhe, Germany; Kiel, Germany; Koln, Germany; Krakow, Poland; Krosno, Poland; Lagos, Nigeria Workplace: remote At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking an Firmware Engineer specialist to join one of our clients ' teams. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you. As a Senior Firmware Engineer you will work within the Firmware Team and be responsible for developing the embedded software for our semiconductor portfolio. You will work closely with other teams’ highly skilled engineers to guarantee a successful firmware design, which is essential for enabling our future products. Responsibilities: Firmware design Firmware verification Desired knowledge: Experience with Linux (and its drivers) and PCIe devices Solid knowledge and experience in dynamic thermal management (DTM) Knowledge on how to use embedded development tools and associated debug tools Knowledge of compilers (clang, gcc) and linkers Experience with low level embedded firmware development Strong programming and scripting skills (C/C++, Assembler, Python, Perl, Bash) Experience in developing and deploying automation flows using scripting languages Experience on CI Experience on SQA Knowledge of revision control methodology and tools (git, svn) Excellent problem-solving and analytical skills, with the ability to troubleshoot and resolve complex physical design issues Strong communication and interpersonal skills to effectively collaborate with cross-functional teams Ability to adapt to a fast-paced work environment and meet project deadlines Preferred/Valued knowledge: Knowledge of RISC-V Knowledge of processor and SoC architectures Knowledge of the JIRA tool

О компании Semidynamics: европейская компания из Барселоны, специализирующаяся на полностью настраиваемых RISC-V процессорных IP ядрах для высокопроизводительных вычислений, ИИ и машинного обучения. Технологии компании включают масштабируемые векторные и тензорные блоки, уникальную архитектуру памяти Gazzillion Misses™ и глубокую конфигурируемость для интеграции в SoC. Компания сотрудничает с ведущими технологическими партнерами и участвует в крупных европейских HPC и open-hardware инициативах. Задачи: — разработка встроенного программного обеспечения для портфеля полупроводниковых продуктов — проектирование прошивки — верификация прошивки Требования: — опыт работы с Linux (и его драйверами) и PCIe устройствами — глубокие знания и опыт в динамическом тепловом управлении (DTM) — умение использовать инструменты разработки встроенного ПО и отладочные инструменты — знание компиляторов clang, gcc и линкеров — опыт разработки низкоуровневой встроенной прошивки — сильные навыки программирования и скриптинга на C/C++, Assembler, Python, Perl, Bash — опыт разработки и внедрения автоматизации с использованием скриптовых языков — опыт работы с CI — опыт в SQA — знание методологии контроля версий и инструментов git, svn — отличные аналитические и проблемно-решающие навыки — хорошие коммуникативные и межличностные навыки для эффективного взаимодействия с кросс-функциональными командами — способность адаптироваться к быстрому темпу работы и соблюдать сроки проектов Желательные знания: — знание RISC-V — знание архитектур процессоров и SoC — знание инструмента JIRA Условия: — возможность работать на переднем крае европейских инноваций в области RISC-V и ИИ процессоров — участие в компании, готовящейся к выпуску 3нм кремния и формирующей будущее инфраструктуры ИИ — сотрудничество в технически сложной среде с доступом к передовым полупроводниковым технологиям — возможности карьерного роста в быстрорастущей глобальной компании — работа в штаб-квартире в Барселоне, технологическом и инновационном центре Европы

Location: Costa Mesa, United States WHAT YOU'LL DO Conduct EMI/EMC testing and analysis on electronic systems and components. Drive product maturity through rapid prototyping, design verification, and qualification activities. Develop and implement design strategies to mitigate EMI/EMC issues. Prepare test plans, reports, and documentation for compliance verification. Collaborate with product design teams to ensure EMC requirements are integrated during the design phase. Identify program EMI/EMC risks and define strategies for reducing risk through the definition of modeling, simulation, or experimental activities. Stay updated on relevant standards (e.g., MIL-STD-461G, MIL-STD-464D, DOD-160, FCC, CISPR, IEC) and regulatory requirements. Conduct field tests and assessments to evaluate product performance in real-world environments. Work in a fast-paced environment, having to juggle multiple concurrent projects and customers. REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Electronics, or a related field. 7+ years of experience in EMI/EMC design and testing. Familiarity with EMC/EMI standards and regulations (e.g., MIL-STD-461G, MIL-STD-464D, RTCA DOD-160, FCC, IEC, CISPR, SAE). Proven expertise in E3 design, analysis, testing and mitigation strategies. Specialized in HERO, HEMP, Lightning Protection, ESD, RF exposure limits and operational electromagnetic compatibility. Proficiency in using EMI/EMC testing equipment (e.g., spectrum analyzers, oscilloscopes, antennas, LISN etc.) Experience with simulation tools (e.g., ANSYS, CST Microwave Studio) for EMI analysis. Strong analytical and troubleshooting skills for identifying and resolving EMI/EMC issues. Excellent verbal and written communication skills for reporting findings and collaborating with teams. Ability to manage multiple projects and meet deadlines in a fast-paced environment. Full understanding of PCB Layout techniques to meet mechanical, electrical, EMI/EMC, and manufacturing requirements. Ability to read and interpret schematics and apply best practices appropriate for each design. Familiarity with standard interfaces such as MIPI, DP, I2C, SPI, PCIe, USB, etc. Must be able to obtain and maintain a DoD Secret Clearance